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EP7211
Preliminary Data Sheet
FEATURES
I Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz at 2.5 V Pentium-based PC
I Performance matching 100-MHz Intel I Socket and register compatible with CL-PS7111 I Ultra low power
-- Designed for applications that require long battery life while using standard AA/AAA batteries or rechargeable cells -- 170 mW at 74 MHz in the Operating State -- 50 mW at 18 MHz in the Operating State -- 15 mW in the Idle State (clock to the CPU stopped, everything else running) -- 10 W in the Standby State (realtime clock `on', everything else stopped)
High-Performance Ultra-LowPower System-on-Chip with LCD Controller OVERVIEW
The EP7211 is designed for ultra-low-power applications such as organizers/PDAs, two-way pagers, smart cellular phones, and industrial hand-held information appliances. The core-logic functionality of the device is built around an ARM720T processor with 8 kbytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU), which allows for Microsoft Windows CE support. The EP7211 also includes a 32-bit Y2K-compliant Real Time Clock (RTC) and comparator. (cont.)
I LCD controller
-- Interfaces directly to a single-scan panel monochrome LCD -- Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments -- Video frame buffer size programmable up to 128 kbytes -- Bits per pixel programmable from 1, 2, or 4
(cont.)
Functional Block Diagram
13-MHZ INPUT 3.6864 MHZ PLL
INTERNAL DATA BUS
D0-D31
ARM720T
32.768 KHZ POR, RUN, RESET, WAKEUP BATOK, EXTPWR PWRFL, BATCHG EINT[1-3], FIQ, MEDCHG FLASHING LED DRIVE PORTS A, B, D (8-BIT) PORT E (3-BIT) KEYBD DRIVERS (0-7) BUZZER DRIVE DC-TO-DC ADCCLK, ADCIN, ADCOUT, SMPCLK, ADCCS SSICLK, SSITXFR, SSITXDA, SSIRXDA, SSIRSFR 32.768-KHZ OSCILLATOR STATE CONTROL POWER MANAGEMENT INTERRUPT CONTROLLER RTC LCD DMA GPIO PWM SSI1 (ADC) MULTIMEDIA CODEC PORT SSI2 CODEC ON-CHIP BOOT ROM TIMER COUNTERS (2) ICE-JTAG LCD CONTROLLER ON-CHIP SRAM 37.5 KBYTES UART1 UART2 8-KBYTE CACHE MMU WRITE BUFFER EXPANSION CONTROL DRAM CONTROLLER
INTERNAL ADDRESS BUS
ARM7TDMI CPU CORE
MEMORY CONTROL BLOCK CL-PS6700 INTFC.
PB[0-1], CS[4-5] EXPCLK, WORD, CS[0-3], EXPRDY, WRITE MOE, MWE, RAS[0-1], CAS[0-3] A[0-27], DRA[0-12] TEST AND DEVELOPMENT LCD DRIVE
IrDA
LED AND PHOTODIODE ASYNC INTERFACE 1 ASYNC INTERFACE 2
APB BRIDGE EPB BUS
Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7851 http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2001 (All Rights Reserved)
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
I ARM720T processor
-- -- -- -- -- --
FEATURES (cont.)
and UCB1200 codecs) (9.216 Mbps operation) ARM7TDMI CPU 8 kbytes of four-way set-associative cache MMU with 64-entry TLB (transition look aside buffer) Write buffer Windows CE enabled Thumb(R) code support enabled
I 27 bits of general-purpose I/O
-- Three 8-bit and one 3-bit GPIO port -- Supports scanning keyboard matrix
I Two UARTs (16550 type)
-- Supports bit rates up to 115.2 kbps -- Contains two 16-byte FIFOs for TX and RX -- UART1 supports modem control signals
I DRAM controller
-- Supports both 16- and 32-bit-wide DRAMs -- EDO support (fast page mode support for 13 MHz and 18 MHz operation only)
I SIR (up to 115.2 kbps) infrared encoder
-- IrDA (Infrared Data Association) SIR protocol encoder can be optionally switched into TX and RX signals of UART1
I ROM/SRAM/FLASH memory control
-- Decodes 4, 5, or 6 separate memory segments of up to 256 Mbytes each -- Each segment can be configured as 8, 16, or 32 bits wide and supports page-mode access -- Programmable access time for conventional ROM/SRAM/Flash memory
I PWM interface
-- Provides two 96-kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC-to-DC converter
I 37.5 kbytes of on-chip SRAM for fast program
execution and/or as a frame buffer
I On-chip ROM; for manufacturing boot-up support I Four synchronous serial interfaces
-- ADC (SSI1) Interface: Master mode only; SPI1 and Microwire12-compatible (128 kbps operation) -- SSI2 Interface: Master/Slave mode; SPI/Microwire2 compatible (512 kbps operation) -- Audio Codec Interface (64 kbps operation) -- Multimedia Codec Port (Interfaces to Philips' UCB1100
I Two timer counters I 208-pin LQFP or 256-ball PBGA packages I Evaluation kit available with BOM, schematics,
sample code, and design database PC Card controllers
I Support for up to two ultra-low-power CL-PS6700 I Dedicated LED flasher pin from RTC I Full JTAG boundary scan and Embedded ICE
support
1 2
SPI is a registered trademark of Motorola. Microwire is a registered trademark of National Semiconductor.
OVERVIEW (cont.)
Power Management
The EP7211 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operating range of 2.5 V-3.3 V. The device has three basic power states:
Operating -- This state is the full performance state. All the clocks and peripheral logic are enabled. Idle -- This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. Standby -- This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake up the processor.
Memory Interfaces
There are two main external memory interfaces. The first one is the ROM/SRAM/Flash-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip selects each decoding 256-Mbyte sections of addressable space. For maximum flexibility, each bank can be specified to be 8, 16, or 32 bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system Flash memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
OVERVIEW (cont.)
use of high-speed 32-bit operations in 16-bit opcodes and yielding industry-leading code density. The second is the programmable 16- or 32-bit-wide DRAM interface that allows direct connection of up to two banks of DRAM, each bank containing up to 256 Mbytes. To assure the lowest possible power consumption, the EP7211 supports self-refresh DRAMs, which are placed in a low-power state by the device when it enters the low-power Standby State. EDO and Fast Page DRAM are supported. A DMA address generator is also provided that fetches video display frame buffer data for the LCD controller from main memory (typically DRAM). The display frame buffer start address is programmable. In addition, the built-in LCD controller can utilize external or internal SRAM for memory, thus eliminating the need for DRAMs.
Serial Interfaces
The EP7211 includes two 16550-type UARTs for RS232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the RX/TX signals to/from one of the
DD[3:0]
CRYSTAL
MOSCIN CS[4] PB0 EXPCLK
CL1 CL2 FM M COL[7:0]
LCD MODULE
D[31:0]
KEYBOARD
PA[7:0] PB[7:0] PD[7:0] PE[2:0]
PC CARD SOCKET
CL-PS6700 PC CARD CONTROLLER
A[27:0] MOE WRITE
EP7211
RAS[1] RAS[0]
x16 DRAM x16 DRAM
x16 DRAM x16 DRAM
CAS[0] CAS[1] CAS[2] CAS[3] CS[0] CS[1]
POR PWRFL BATOK EXTPWR BATCHG RUN WAKEUP DRIVE[1:0] FB[1:0] SSICLK SSITXFR SSITXDA SSIRXDA
POWER SUPPLY UNIT AND COMPARATORS
DC INPUT
BATTERY
DC-TO-DC CONVERTERS
x16 FLASH x16 FLASH
x16 ROM x16 ROM
CS[n] WORD
CODEC
LEDDRV PHDIN RXD1/2 TXD1/2 DSR CTS DCD ADCCLK ADCCS ADCOUT ADCIN SMPCLK
IR LED AND PHOTODIODE
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
2x RS-232 TRANSCEIVERS
CS[2] CS[3]
ADDITIONAL I/O
BUFFERS AND LATCHES
ADC
DIGITIZER
Figure 1-1. A EP7211-Based System
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
OVERVIEW (cont.)
UARTs to enable these signals to drive an infrared communication interface directly. Four synchronous serial interfaces (codec, SSI1, SSI2, and MCP) are provided. Three of them (codec, SSI2, and MCP) are multiplexed onto a single set of interface pins. The full-duplex codec interface allows direct connection of a standard audio codec chip to the EP7211, allowing storage and playback of sound. SSI2 supports both master and slave mode. SSI1 supports master mode only. Both SSI1 and SSI2 support two industry-standard protocols (SPI and Microwire) for interfacing standard devices (e.g., Max148/9 or AD7811/12 ADC), and for allowing peripheral expansion (e.g., a digitizer pen). A Multimedia Codec Port (MCP) can be used to communicate with a multi-functional codec device like the Philips UCB1100.
System Design
As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7211 completes a low-power system solution. All necessary interface logic is integrated on-chip.
Development Boards
Cirrus Logic offers an evaluation and development environment for the EP7211 in the form of the EDB7211-2 Development Kit. The EDB7211-2 development kit is a complete development platform with access to the features and capabilities of the EP7211. The kit provides the tools required for developing and testing the design of a highly integrated EP7211 system.
Packaging
The EP7211 is available in a 208-pin LQFP package and a 256-ball PBGA package.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
TABLE OF CONTENTS
1. CONVENTIONS........................................................................................................................11
1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 Acronyms and Abbreviations................................................................................................................... 11 Units of Measurement .............................................................................................................................12 General Conventions...............................................................................................................................12 Pin Description Conventions ...................................................................................................................12 Pin Diagrams...........................................................................................................................................13 Pin Descriptions ......................................................................................................................................14 2.2.1 External Signal Functions...........................................................................................................15 256-Ball PBGA Ball Listing......................................................................................................................20 2.3.1 PBGA Ground Connections .......................................................................................................25 208-Pin LQFP Pin Listing ........................................................................................................................26 JTAG Pin Ordering for 208-Pin LQFP Package ......................................................................................31
2. PIN INFORMATION..................................................................................................................13
3. FUNCTIONAL DESCRIPTION.................................................................................................34
Main Functional Blocks ...........................................................................................................................35 CPU Core ................................................................................................................................................37 Interrupt Controller ..................................................................................................................................37 3.3.1 Interrupt Latencies in Different States ........................................................................................39 3.3.1.1 Operating State ..........................................................................................................39 3.3.1.2 Idle State ....................................................................................................................40 3.3.1.3 Standby State .............................................................................................................40 3.4 Memory and I/O Expansion Interface ......................................................................................................42 3.5 EP7211 Boot ROM ..................................................................................................................................43 3.6 CL-PS6700 PC Card Controller Interface ...............................................................................................44 3.7 DRAM Controller with EDO Support .......................................................................................................47 3.8 Serial Interfaces ......................................................................................................................................51 3.8.1 Codec Sound Interface...............................................................................................................52 3.8.1.1 Codec Interrupt Timing...............................................................................................52 3.8.2 MCP Interface ............................................................................................................................53 3.8.2.1 MCP Operation ..........................................................................................................54 3.8.2.2 MCP Frame Format ...................................................................................................54 3.8.2.3 Audio and Telecom Sample Rates and Data Transfer ...............................................56 3.8.2.4 MCP FIFO Operation .................................................................................................58 3.8.2.5 MCP Codec Control Register Data Transfer ..............................................................59 3.8.3 ADC Interface -- Master Mode Only SSI1 (Synchronous Serial Interface) ...............................60 3.8.4 Master/Slave SSI2 (Synchronous Serial Interface 2) .................................................................61 3.8.4.1 Read Back of Residual Data ......................................................................................62 3.8.4.2 Support for Asymmetric Traffic ...................................................................................63 3.8.4.3 Continuous Data Transfer ..........................................................................................63 3.8.4.4 Discontinuous Clock...................................................................................................63 3.8.4.5 Error Conditions .........................................................................................................64 3.8.4.6 Clock Polarity .............................................................................................................64 3.9 LCD Controller with Support for On-Chip Frame Buffer ..........................................................................64 3.10 Internal UARTs (Two) and SIR Encoder ..................................................................................................67 3.11 Timer Counters........................................................................................................................................67 3.11.1 Free Running Mode....................................................................................................................68
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3.12 3.13 3.14 3.15 3.16 3.17
3.18 3.19 3.20 3.21 3.22
3.11.2 Prescale Mode ...........................................................................................................................68 Realtime Clock ........................................................................................................................................68 Dedicated LED Flasher ...........................................................................................................................68 Two PWM Interfaces ...............................................................................................................................69 State Control............................................................................................................................................69 Resets .....................................................................................................................................................72 Clocks......................................................................................................................................................73 3.17.1 On-Chip PLL...............................................................................................................................73 3.17.2 External Clock Input (13 MHz) ...................................................................................................74 Dynamic Clock Switching When in the PLL Clocking Mode....................................................................75 Endianness..............................................................................................................................................75 Maximum EP7211-Based System ...........................................................................................................77 Boundary Scan........................................................................................................................................78 In-Circuit Emulation .................................................................................................................................79 3.22.1 Introduction.................................................................................................................................79 3.22.2 Functionality ...............................................................................................................................79
4. MEMORY MAP .........................................................................................................................80 5. REGISTER DESCRIPTIONS ...................................................................................................81
5.1 Internal Registers ....................................................................................................................................81 5.1.1 PADR Port A Data Register........................................................................................................85 5.1.2 PBDR Port B Data Register .......................................................................................................85 5.1.3 PDDR Port D Data Register .......................................................................................................85 5.1.4 PADDR Port A Data Direction Register ...................................................................................... 85 5.1.5 PBDDR Port B Data Direction Register......................................................................................85 5.1.6 PDDDR Port D Data Direction Register .....................................................................................85 5.1.7 PEDR Port E Data Register .......................................................................................................86 5.1.8 PEDDR Port E Data Direction Register......................................................................................86 SYSTEM Control Registers.....................................................................................................................86 5.2.1 SYSCON1 The System Control Register 1 ................................................................................86 5.2.2 SYSCON2 System Control Register 2 .......................................................................................89 5.2.3 SYSCON3 System Control Register 3 .......................................................................................91 5.2.4 SYSFLG -- The System Status Flags Register .........................................................................92 5.2.5 SYSFLG2 System Status Register 2..........................................................................................94 Interrupt Registers...................................................................................................................................95 5.3.1 INTSR1 Interrupt Status Register 1............................................................................................95 5.3.2 INTMR1 Interrupt Mask Register 1.............................................................................................97 5.3.3 INTSR2 Interrupt Status Register 2............................................................................................97 5.3.4 INTMR2 Interrupt Mask Register 2.............................................................................................98 5.3.5 INTSR3 Interrupt Status Register 3............................................................................................98 5.3.6 INTMR3 Interrupt Mask Register 3.............................................................................................99 Memory Configuration Registers.............................................................................................................99 5.4.1 MEMCFG1 Memory Configuration Register 1............................................................................99 5.4.2 MEMCFG2 Memory Configuration Register 2..........................................................................100 5.4.3 DRFPR DRAM Refresh Period Register ..................................................................................102 Timer/Counter Registers .......................................................................................................................103 5.5.1 TC1D Timer Counter 1 Data Register ......................................................................................103 5.5.2 TC2D Timer Counter 2 Data Register ......................................................................................103 5.5.3 RTCDR Realtime Clock Data Register.....................................................................................103 5.5.4 RTCMR Realtime Clock Match Register ..................................................................................103 DS352PP3 JUL 2001
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5.3
5.4
5.5
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.6 5.7 5.8 5.9
5.10
5.11 5.12 5.13
5.14
5.15
5.16
LEDFLSH Register................................................................................................................................104 PMPCON Pump Control Register .........................................................................................................105 CODR -- The CODEC Interface Data Register ....................................................................................106 UART Registers ....................................................................................................................................106 5.9.1 UARTDR1-2 UART1-2 Data Registers ...................................................................................106 5.9.2 UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers...................................................107 LCD Registers .......................................................................................................................................108 5.10.1 LCDCON -- The LCD Control Register ...................................................................................108 5.10.2 PALLSW Least Significant Word -- LCD Palette Register....................................................... 110 5.10.3 PALMSW Most Significant Word -- LCD Palette Register ....................................................... 110 5.10.4 FBADDR LCD Frame Buffer Start Address .............................................................................. 111 SSI Register .......................................................................................................................................... 111 5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register ..................................................... 111 STFCLR Clear all `Start Up Reason' flags location ............................................................................... 113 `End Of Interrupt' Locations................................................................................................................... 113 5.13.1 BLEOI Battery Low End of Interrupt ......................................................................................... 113 5.13.2 MCEOI Media Changed End of Interrupt ................................................................................. 113 5.13.3 TEOI Tick End of Interrupt Location ......................................................................................... 113 5.13.4 TC1EOI TC1 End of Interrupt Location .................................................................................... 113 5.13.5 TC2EOI TC2 End of Interrupt Location .................................................................................... 113 5.13.6 RTCEOI RTC Match End of Interrupt ....................................................................................... 113 5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt ..................................................... 114 5.13.8 COEOI Codec End of Interrupt Location .................................................................................. 114 5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................................... 114 5.13.10 SRXEOF End of Interrupt Location .......................................................................................... 114 State Control Registers ......................................................................................................................... 114 5.14.1 STDBY Enter the Standby State Location ................................................................................ 114 5.14.2 HALT Enter the Idle State Location .......................................................................................... 114 SS2 Registers ....................................................................................................................................... 115 5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ............................................................ 115 5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte .................................................. 115 MCP Register Definitions ...................................................................................................................... 115 5.16.1 MCP Control Register .............................................................................................................. 116 5.16.1.1 Audio Sample Rate Divisor (ASD) ........................................................................... 116 5.16.1.2 Telecom Sample Rate Divisor (TSD) ....................................................................... 117 5.16.1.3 Multimedia Communications Port Enable (MCE) ..................................................... 117 5.16.1.4 A/D Sampling Mode (ADM) ...................................................................................... 118 5.16.1.5 MCP Interrupt Generation ........................................................................................ 118 5.16.1.6 Telecom Transmit FIFO Interrupt Mask (TTM) ......................................................... 118 5.16.1.7 Telecom Receive FIFO Interrupt Mask (TRM) ......................................................... 118 5.16.1.8 Audio Transmit FIFO Interrupt Mask (ATM) ............................................................. 119 5.16.1.9 Audio Receive FIFO Interrupt Mask (ARM) ............................................................. 119 5.16.1.10 Loop Back Mode (LBM) ........................................................................................... 119 5.16.2 MCP Data Registers.................................................................................................................121 5.16.2.1 MCP Data Register 0 ...............................................................................................121 5.16.2.2 MCP Data Register 1 ...............................................................................................123 5.16.2.3 MCP Data Register 2 ...............................................................................................125 5.16.3 MCP Status Register ................................................................................................................127
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5.16.3.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)...................................................................................................................127 5.16.3.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt) .127 5.16.3.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt) ..................................................................................................127 5.16.3.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrupt)...................................................................................................................128 5.16.3.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, non-maskable interrupt).128 5.16.3.6 Audio Receive FIFO Overrun Status (ARO) (read/write, non-maskable interrupt)...128 5.16.3.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, non-maskable interrupt)...................................................................................................................128 5.16.3.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, non-maskable interrupt)...................................................................................................................128 5.16.3.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, non-interruptible) ..................129 5.16.3.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, non-interruptible) ..............129 5.16.3.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible) ..............129 5.16.3.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, non-interruptible) ..........129 5.16.3.13 Codec Write Completed Flag (CWC) (read-only, non-interruptible) .........................129 5.16.3.14 Codec Read Completed Flag (CRC) (read-only, non-interruptible)..........................129 5.16.3.15 Audio Codec Enabled Flag (ACE) (read-only, non-interruptible)..............................130 5.16.3.16 Telecom Codec Enabled Flag (TCE) (read-only, non-interruptible)..........................130
6. ELECTRICAL SPECIFICATIONS......................................................................................... 133
6.1 6.2 6.3 6.4 6.5 7.1 7.2 7.3 7.4 7.5 8.1 8.2 Absolute Maximum Ratings...................................................................................................................133 Recommended Operating Conditions ...................................................................................................133 DC Characteristics ................................................................................................................................133 AC Characteristics.................................................................................................................................135 I/O Buffer Characteristics ......................................................................................................................150 Oscillator and PLL Bypass Mode ..........................................................................................................151 Oscillator and PLL Test Mode ...............................................................................................................151 Debug/ICE Test Mode ..........................................................................................................................152 Hi-Z (System) Test Mode......................................................................................................................152 Software Selectable Test Functionality.................................................................................................152 EP7211 256-Ball PBGA (17 x 17 x 1.53-mm Body) Dimensions ..........................................................154 208-Pin LQFP Package Outline Drawing .............................................................................................155
7. TEST MODES ........................................................................................................................ 151
8. PACKAGE SPECIFICATIONS.............................................................................................. 154
9. ORDERING INFORMATION ................................................................................................. 156 10. APPENDIX A: BOOT CODE................................................................................................. 157 11. INDEX..................................................................................................................................... 162
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
LIST OF TABLES
Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 4-1. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-15. Table 5-16. Table 5-17. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 7-3. SSI/Codec/MCP Pin Multiplexing.................................................................................................... 18 256-Ball PBGA Ball Listing ............................................................................................................ 20 PBGA Balls to Connect to Ground (VSS) ........................................................................................ 23 208-Pin LQFP Numeric Pin Listing ................................................................................................. 24 JTAG Pin Ordering for 208-Pin LQFP Package ............................................................................. 28 Interrupt Allocation in First Interrupt Register ................................................................................. 35 Interrupt Allocation in Second Interrupt Register ............................................................................ 36 Interrupt Allocation in Third Interrupt Register ................................................................................ 36 External Interrupt Source Latencies................................................................................................ 38 Boot Options ................................................................................................................................... 40 Chip Select Address Ranges After Boot From On-Chip Boot ROM ............................................... 40 CL-PS6700 Memory Map ............................................................................................................... 41 Space Field Decoding ..................................................................................................................... 42 Physical to DRAM Address Mapping .............................................................................................. 45 DRAM Address Mapping When Connected to an External 32-Bit DRAM Memory System ........... 46 DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System.............................................. 47 Serial Interface Options .................................................................................................................. 48 Serial-Pin Assignments................................................................................................................... 48 ADC Interface Operation Frequencies............................................................................................ 57 Peripheral Status in Different Power Management States .............................................................. 67 Effect of Endianness on Read Operations...................................................................................... 73 Effect of Endianness on Write Operations ...................................................................................... 73 Instructions Supported in JTAG Mode ............................................................................................ 75 EP7211 Memory Map ..................................................................................................................... 77 CL-PS7111-Compatible................................................................................................................... 79 Internal I/O Memory Locations (EP7211 Only) ............................................................................... 81 Port Byte Addresses in Big Endian Mode ....................................................................................... 81 Values of the Bus Width Field ......................................................................................................... 97 Values of the Wait State Field at 13 MHz and 18 MHz ................................................................... 98 Values of the Wait State Field at 36 MHz........................................................................................ 98 LED Flash Rates........................................................................................................................... 101 LED Duty Ratio ............................................................................................................................. 101 Sense of PWM control lines.......................................................................................................... 102 UART Bit Rates Running from the PLL Clock............................................................................... 104 UART Bit Rates Running from an External 13.0 MHz Clock ........................................................ 104 Grey Scale Value to Color Mapping.............................................................................................. 107 MCP Control Register ................................................................................................................... 117 MCP Data Register 0 .................................................................................................................... 120 MCP Data Register 1 .................................................................................................................... 121 MCP Data Register 2 .................................................................................................................... 123 MCP Control, Data and Status Register Locations ....................................................................... 128 DC Characteristics ........................................................................................................................ 130 AC Timing Characteristics ............................................................................................................ 132 Timing Characteristics .................................................................................................................. 133 I/O Buffer Output Characteristics .................................................................................................. 147 EP7211 Hardware Test Modes ..................................................................................................... 148 Oscillator and PLL Test Mode Signals .......................................................................................... 149 Software Selectable Test Functionality ......................................................................................... 150
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
LIST OF FIGURES
Figure 1-1. Figure 2-1. Figure 2-2. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Figure 6-14. Figure 6-15. A EP7211-Based System................................................................................................................... 3 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ...............................................................13 256-Ball Plastic Ball Grid Array Diagram ..........................................................................................14 EP7211 Block Diagram .....................................................................................................................37 Codec Interrupt Timing .....................................................................................................................52 Data Format of MCP Subframe 0 .....................................................................................................55 MCP Packet Organization ................................................................................................................55 Audio Codec Enable Timing .............................................................................................................57 Format for the Audio and Telecom FIFOs.........................................................................................59 SSI2 Port Directions in Slave and Master Mode...............................................................................61 Residual Byte Reading .....................................................................................................................63 Video Buffer Mapping .......................................................................................................................66 State Diagram ...................................................................................................................................72 CLKEN Timing Entering the Standby State.......................................................................................74 CLKEN Timing Leaving the Standby State ......................................................................................75 A Maximum EP7211 Based System .................................................................................................77 MCP Data Register 0: MCDR0 .......................................................................................................122 MCP Data Register 1: MCDR1 .......................................................................................................124 MCP Data Register 2: MCDR2 .......................................................................................................126 MCP Status Register: MCSR .........................................................................................................131 Expansion and ROM Timing ...........................................................................................................137 Expansion and ROM Sequential Read Timings..............................................................................138 Expansion and ROM Write Timings ................................................................................................139 DRAM Read Cycles at 13 MHz and 18.432 MHz ........................................................................... 140 DRAM Read Cycles at 36 MHz ......................................................................................................141 DRAM Write Cycles at 13 MHz and 18 MHz ..................................................................................142 DRAM Write Cycles at 36 MHz.......................................................................................................143 Video Quad Word Read from DRAM at 13 MHz and 18 MHz ........................................................144 Quad Word Read from DRAM at 36 MHz.......................................................................................145 DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz....................................................146 DRAM CAS Before RAS Refresh Cycle at 36 MHz ........................................................................ 147 LCD Controller Timings...................................................................................................................148 SSI Interface for AD7811/2 .............................................................................................................148 SSI Timing Interface for MAX148/9 ................................................................................................149 SSI2 Interface Timings....................................................................................................................149
10
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
1. CONVENTIONS
This section presents acronyms, abbreviations, units of measurement, and conventions used in this data book. 1.1 Acronyms and Abbreviations The following table lists abbreviations and acronyms used in this data book.
Acronym/ Abbreviation
AC A/D ADC codec CMOS CPU D/A DC DMA DRAM EPB FCS FIFO GPIO ICT IR IrDA JTAG LCD LED LSB
Definition
alternating current analog-to-digital analong-to-digital converter coder/decoder complementary metal oxide semiconductor central processing unit digital-to-analog direct current direct-memory access dynamic random access memory embedded peripheral bus frame check sequence first in/first out general purpose I/O in circuit test infrared Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode least significant bit
Acronym/ Abbreviation
MIPS LQFP MMU MSB PBGA PCB PDA PIA PLL PSU p/u RAM RISC ROM RTC SIR SRAM SSI TAP TLB UART
Definition
millions of instructions per second low profile quad flat pack memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant peripheral interface adapter phase locked loop power supply unit pull-up resistor random access memory reduced instruction set computer read-only memory realtime clock slow (9600-115.2 kbps) infrared static random access memory synchronous serial interface test access port translation look aside buffer universal asynchronous receiver transmitter
DS352PP3 JUL 2001
Conventions
11
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
1.2
\
Units of Measurement
Unit of Measure
degree Celsius hertz (cycle per second) kilobits per second kilobyte (1,024 bytes) kilohertz kilohm megabits (1,048,576 bits) per second megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) microampere
Symbol
Symbol
F W s mA mW ms ns V W microfarad microwatt
Unit of Measure
C
Hz kbits/s kbyte kHz k Mbps Mbyte MHz A
microsecond (1,000 nanoseconds) milliampere milliwatt millisecond (1,000 microseconds) nanosecond volt watt
1.3
General Conventions Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For example, 14h and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an h or quotation marks are decimal. Registers are referred to by acronym, as listed in the tables on the previous page, with bits listed in brackets MSB-to-LSB separated by a colon (:) (for example, CODR[7:0]), or LSB-to-MSB separated by a hyphen (for example, CODR[0-2]). The use of `tbd' indicates values that are `to be determined', `n/a' designates `not available', and `n/c' indicates a pin that is a `no connect'.
1.4
Pin Description Conventions Abbreviations used for signal directions in Section 2 are listed in the following table:
Abbreviation Direction
Input Output Input or Output
I O I/O
12
Conventions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2. PIN INFORMATION
2.1 Pin Diagrams
NURESET NMEDCHG/NBROM NPOR BATOK NEXTPWR NBATCHG D[7] VSSIO A[7] D[8] A[8] D[9] A[9] D[10] A[10] D[11] VSSIO VDDIO A[11] D[12] A[12] D[13] A[13] D[14] A[14] D[15] A[15]/DRA[12] D[16] A[16]/DRA[11] D[17] A[17]/DRA[10] NTRST VSSIO VDDIO D[18] A[18]/DRA[9] D[19] A[19]/DRA[8] D[20] A[20]/DRA[7] VSSIO D[21] A[21]/DRA[6] D[22] A[22]/DRA[5] D[23] A[23]/DRA[4] D[24] VSSIO VDDIO A[24]/DRA[3] HALFWORD 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Figure 2-1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
NCS[5] VDDIO VSSIO EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/PRDY[2] PB[0]/PRDY[1] VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD DSR NTEST[1] NTEST[0] EINT[3] NEINT[2] NEINT[1] NEXTFIQ PE[2]/CLKSEL PE[1]BOOTSEL[1] PE[0]BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP NPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE VSSIO VDDIO CL[2] CL[1] FRM M DD[3] DD[2] VSSIO DD[1] DD[0] NRAS[1] NRAS[0] NCAS[3] NCAS[2] VDDIO VSSIO NCAS[1] NCAS[0] NMWE NMOE VSSIO NCS[0] NCS[1] NCS[2] NCS[3] NCS[4]
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
EP7211
208-Pin LQFP
(Top View)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
D[25] A[25]/DRA[2] D[26] A[26]/DRA[1] D[27] A[27]/DRA[0] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE NADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFLSH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6] PD[7]
DS352PP3 JUL 2001
Pin Information
13
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 A B C D E F G H J K L M N P R T
256-Ball PBGA
(Bottom View)
(Call Factory for Availability)
Figure 2-2. 256-Ball Plastic Ball Grid Array Diagram
2.2
Pin Descriptions This table describes the function of all the external signals to the EP7211. Note that all output signals are tri-stateable to enable the Hi-Z test modes to be supported.
14
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2.2.1
External Signal Functions
Signal Name
D[0-31]
Function
Data bus
Signal
I/O
Description
32-bit system data bus for DRAM, ROM/SRAM/Flash, and memory mapped I/O expansion Least significant 15 bits of system byte address during ROM/SRAM/Flash and expansion cycles 13-bit multiplexed DRAM word address during DRAM cycles or address bits 16 to 27 of system byte address during ROM/SRAM/Flash and expansion cycles - Whenever the EP7211 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are powerdown from draining current. Also, the internal peripheral's signals get set to their Reset State. - For additional power saving, the multiplexed DRAM address lines are output on the high order ROM address lines where the lightest loading is expected. DRAM RAS outputs to DRAM banks 0 to 1 DRAM CAS outputs for bytes 0 to 3 within 32-bit word DRAM, ROM/SRAM/Flash, and expansion output enable DRAM, ROM/SRAM/Flash, and expansion write enable Expansion channel I/O strobes; active low SRAM-like chip selects for expansion Expansion channel I/O strobes; active low CS for expansion or for CL-PS6700 select Expansion channel ready; external expansion devices drive this low to extend the bus cycle Transfer direction, low during reads, high during writes from the EP7211 Word access enable; driven high during word-wide cycles, low during bytewide cycles Half-Word access flag; driven high to denote upper half-word accesses Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input
A[0-14]
O
A[15]/ DRA[12]- A[27]/DRA[0] Address bus
O
NRAS[0-1] NCAS[0-3] NMOE NMWE NCS[0-3]
O I/O O O O
NCS[4-5] Memory and Expansion Interface
O
EXPRDY
I/O
WRITE
O
WORD
O
HALFWORD EXPCLK
O I/O
DS352PP3 JUL 2001
Pin Information
15
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Function
Signal Name
NMEDCHG/ BROM
Signal
I
Description
Media changed input; active low, deglitched -- it is used as a general purpose FIQ interrupt during normal operation. It is also used on power up to configure the processor to either boot from the internal Boot ROM, or from external memory. When low, the chip will boot from the internal Boot ROM. External active low fast interrupt request input External active high interrupt request input Two general purpose, active low interrupt inputs Power fail input; active low deglitched input to force system into the Standby State Main battery OK input; falling edge generates a FIQ, a low level in the Standby State inhibits system start up; deglitched input External power sense; must be driven low if the system is powered by an external source New battery sense; driven low if battery voltage falls below the "no-battery" threshold; it is a deglitched input Power-on reset input; active low input completely resets the entire system; must be held active for at least two clock cycles to be detected cleanly This pin is programmed to either output the RUN signal or the CLKEN signal. The CLKENSL bit is used to configure this pin. When RUN is selected, the pin will be high when the system is active or idle, low while in the Standby State. When CLKEN is selected, the pin will only be driven low when in the Standby State.
Interrupts NEXTFIQ EINT3 NEINT[1-2] NPWRFL I I I I
BATOK Power Management NEXTPWR
I
I
NBATCHG
I
NPOR
I
RUN/CLKEN
State Control
WAKEUP
I
Wake up deglitched input signal; rising edge forces system into the Operating State; active after a power-on reset User reset input; active low deglitched input from user reset button. This pin is also latched upon the rising edge of NPOR and read along with the input pins NTEST[0-1] to force the device into special test modes. MCP/Codec/SSI2 clock signal MCP/Codec/SSI2 serial data output frame/synchronization pulse output MCP/Codec/SSI2 serial data output MCP/Codec/SSI2 serial data input SSI2 serial data input frame/synchronization pulse
NURESET
I
SSICLK MCP, Codec or SSI2 Interface (See Note) SSITXFR SSITXDA SSIRXDA SSIRXFR
I/O I/O O I I/O
16
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Function
Signal Name
ADCCLK
Signal
O O O I O O I O I I I I I/O Serial clock output Chip select for ADC interface Serial data output Serial data input Sample clock output
Description
ADC Interface (SSI1)
NADCCS ADCOUT ADCIN SMPCLK LEDDRV PHDIN
Infrared LED drive output (UART1) Photo diode input (UART1) RS232 UART1 and 2 TX outputs RS232 UART1 and 2 RX inputs RS232 DSR input RS232 DCD input RS232 CTS input LCD serial display data; pins can be used on power up to read the ID of some LCD modules LCD line clock LCD pixel clock LCD frame synchronization pulse output LCD AC bias drive Keyboard column drives Buzzer drive output LED flasher driver -- multiplexed with Port D Bit 0. This pin can provide up to 4 mA of drive current. Port A I/O (Bit 6 for boot clock option, Bit 7 for CL-PS6700 PRDY input); also used as keyboard row inputs Port B I/O. All eight Port B bits can be used as GPIOs. When the PC CARD1 or 2 control bits in the SYSCON2 register are deasserted, PB[0] and PB[1] are available for GPIO. When asserted, these port bits are used as the PRDY signals for connected CL-PS6700 PC Card Host Adapter devices.
IrDA and RS232 Interfaces
TXD[1-2] RXD[1-2] DSR DCD CTS DD[0-3]
CL1 LCD CL2 FRM M COL[0-7] Keyboard & Buzzer drive LED Flasher BUZ PD[0]/ LEDFLSH PA[0-7]
O O O O O O O
I/O
General Purpose I/O
PB[0]/PRDY1 PB[1]/PRDY2 PB[2-7]
I/O
PD[0-7]
I/O
Port D I/O
DS352PP3 JUL 2001
Pin Information
17
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Function
Signal Name
PE[0]/ BOOTSEL0 PE[1]/ BOOTSEL1
Signal
I/O
Description
Port E I/O (3 bits only). Can be used as general purpose I/O during normal operation. During power-on reset, PE[0] and PE[1] are inputs and are latched by the rising edge of NPOR to select the memory width that the EP7211 will use to read from the boot code storage device (e.g., external 8-bitwide Flash bank). During power-on reset, PE[2] is latched by the rising edge of NPOR to select the clock mode of operation (i.e., either the PLL or external 13 MHz clock mode). PWM drive outputs. These pins are inputs on power up to determine what polarity the output of the PWM should be when active. Otherwise, these pins are always an output. PWM feedback inputs JTAG data in JTAG data out JTAG mode select JTAG clock JTAG async reset Test mode select inputs. These pins are used in conjunction with the power-on latched state of NURESET. Main 3.6864 MHz oscillator for 18.432MHz-73.728 MHz PLL
I/O
PE[2]/ CLKSEL
I/O
DRIVE[0-1] PWM Drives FB[0-1] TDI TDO Boundary Scan TMS TCLK TNRST Test NTEST[0-1]
I/O
I I O I I I I
MOSCIN MOSCOUT Oscillators RTCIN RTCOUT
I O I O
Realtime clock 32.768 kHz oscillator
NOTE: .
See table below for pin assignment and direction following pin multiplexing.
Table 2-1. SSI/Codec/MCP Pin Multiplexing
SSI2
SSICCLK SSITXFR SSITXDA SSIRXDA SSIRXFR
Codec
PCMCLK PCMSYNC PCMOUT PCMIN p/u*
MCP
SIBCLK SIBSYNC SIBDOUT SIBDIN p/u*
Direction
I/O I/O Output Input I/O
Strength
1 1 1
1
* p/u = use an ~10 k pull-up
18
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2 (Section 5.2.2 SYSCON2 System Control Register 2). The choice between the SSI2, codec, and the MCP is controlled by the MCPSEL bit in SYSCON3 (Section 5.2.3 SYSCON3 System Control Register 3).
NOTE: All deglitched inputs are via the 16.384 kHz clock. Therefore, the input signal must be active for at least ~61 s to be detected cleanly.
The following output pins are implemented as bi-directional pins to enable the output side of the pad to be monitored and hence provide more accurate control of timing or duration: RUN NCAS[3:0] Drive 0 and 1 DD[3:0] The RUN pin is looped back in to skew the address and data bus from each other. The NCAS pins are looped back into the EP7211 to be used as the actual clock source for the data to be latched internally. Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be when active. DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules.
DS352PP3 JUL 2001
Pin Information
19
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2.3
256-Ball PBGA Ball Listing
Table 2-2. 256-Ball PBGA Ball Listing
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Name
WAKEUP VSSIO NURESET VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO NPOR NEXTPWR WRITE EXPRDY VSSIO VDDIO NCS[2] NMWE NRAS[0] CL[2] VSSCORE D[4] NPWRFL
Type
I Pad ground I Pad power I Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground I I O I Pad ground Pad power O O O O Core ground I/O I
Ball Location
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
Name
VDDIO NCS[4] NCS[1] NCAS[0] NCAS[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO NCS[5] VDDIO NCS[3] NMOE VDDIO NRAS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5]
Type
Pad power O O O O O O Pad power I/O I/O O Pad power O O Oscillator power Pad ground O Pad power O O Pad power O O O Core power I/O O O O
20
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6
Name
MOSCIN VDDIO VSSIO D[7] D[8] RXD[2] PB[7] TDI WORD VSSIO NCS[0] NCAS[2] FRM A[0] D[5] VSSOSC VSSIO NMEDCHG/NBROM VDDIO D[9] D[10] PB[5] PB[3] VSSIO TXD[2] RUN/CLKEN VSSIO NCAS[1] DD[3]
Type
I Pad power Pad ground I/O I/O I I I O Pad ground O O O O I/O Oscillator ground Pad ground I Pad power I/O I/O I I Pad ground O O Pad ground O O
Name
A[1] D[6] VSSRTC BATOK NBATCHG VSSIO D[11] VDDIO PB[1]/PRDY[2] VDDIO TDO PB[4] PB[6] VSSCORE VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] PA[7] PA[5] VSSIO PA[4] PA[6] PB[0]/PRDY[1]
Type
O I/O RTC ground I I Pad ground I/O Pad power I Pad power O I I Core ground RTC ground O I/O RTC ground O O O Pad ground I/O I/O I I Pad ground I I I
DS352PP3 JUL 2001
Pin Information
21
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2
Name
PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13] VSSIO D[14] D[15] PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/DRA[10] A[16]/DRA[11] A[15]/DRA[12] A[14] TNRST D[16] D[17] LEDDRV PHDIN VSSIO DCD
Type
I RTC ground RTC ground O O O O Pad ground I/O I/O I I Pad ground I I O I RTC ground RTC ground O O O O I I/O I/O O I Pad ground I
Name
NTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO RXD[1] DSR VDDIO NEINT[1] PE[2]/CLKSEL VSSRTC PD[0]/LEDFLSH VSSCORE COL[6] D[31] VSSRTC A[22]/DRA[5] A[21]/DRA[6] VSSIO A[18]/DRA[9] A[19]/DRA[8] NTEST[0] NEINT[2]
Type
I I RTC ground I O I I/O I/O I/O Pad ground Pad power Pad power I I Pad power I I RTC ground I/O Core ground O I/O RTC ground O O Pad ground O O I I
22
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13
Name
VDDIO PE[0]/BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/DRA[4] VDDIO A[20]/DRA[7] D[21] NEXTFIQ PE[1]/BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23]
Type
Pad power I I Pad power I/O I/O I O I/O Pad ground O Pad power O I/O I I Pad ground Pad power I/O I/O I/O O O O I/O I/O O Pad ground I/O I/O
Name
VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO RTCIN VDDIO PD[4] PD[1] SSITXDA NADCCS VDDIO ADCOUT COL[7]/PTOUT COL[3] COL[1] D[30] A[27]/DRA[0]
Type
32 K oscillator ground O Pad ground Pad ground Pad power Pad ground Pad ground Pad power Pad ground Pad power Pad ground Pad ground Pad power Pad ground I/O Pad power O Pad power I/O I/O O O Pad power O O O O I/O O
DS352PP3 JUL 2001
Pin Information
23
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-2. (cont.)256-Ball PBGA Ball Listing
Ball Location
R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Name
A[25]/DRA[2] VDDIO A[24]/DRA[3] VDDRTC PD[7] PD[6] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/DRA[1] D[25] VSSIO
Type
O Pad power O 32 K oscillator power I/O I/O I/O I/O - Core power I/O I O Pad power O I/O O I/O Pad power
24
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2.4
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
208-Pin LQFP Pin Listing
Table 2-3. 208-Pin LQFP Numeric Pin Listing
Signal
NCS[5] VDDIO VSSIO EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/ PRDY[2] PB[0]/ PRDY[1] VDDIO TDO
Type
Out Pad Pwr Pad Gnd I/O Out Out I/O I/O Out In In Pad Gnd I/O I/O I/O I/O I/O I/O I/O I/O Pad Pwr Out
Strength
1
Reset State
Low
Pin No.
27 28 29
Signal
PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD DSR NTEST[1] NTEST[0] EINT[3] NEINT[2] NEINT[1] NEXTFIQ PE[2]/ CLKSEL PE[1]/ BOOTSEL[1] PE[0]/ BOOTSEL[0] VSSRTC
Type
I/O I/O I/O I/O Out Out Pad Gnd In In In In In In In In In In In I/O I/O I/O VDDRTC VSSRTC 32 K Osc Gnd 32 K Osc 32 K Osc 32 K Osc power
Strength
1 1 1 1 1 1 1
Reset State
Input Input Input Input Low High High
1 1 1 1 1 1 High Low Low Low
30 31 32 33 34 35 36
with p/u*
37 38
1 1 1 1 1 1 1 1
Input Input Input Input Input Input Input Input
39 40 41 42 43 44 45 46 47
With p/u* With p/u*
High High
1 1 1
Input Input Input
1
Tristate
48
23 24 25
PA[7] PA[6] PA[5]
I/O I/O I/O
1 1 1
Input Input Input
49 50 51
RTCOUT RTCIN VDDRTC
X X
DS352PP3 JUL 2001
Pin Information
25
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-3. 208-Pin LQFP Numeric Pin Listing (cont.)
Pin No.
26 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
Signal
PA[4] PD[7] PD[6] PD[5] PD[4] VDDIO TMS PD[3] PD[2] PD[1] PD[0]/ LEDFLSH SSICLK VSSIO SSITXFR SSITXDA SSIRXDA SSIRXFR ADCIN NADCCS VSSCORE
Type
I/O I/O I/O I/O I/O Pad Pwr In I/O I/O I/O I/O I/O Pad Gnd I/O Out In I/O In Out VSSCO REVDD COREC ore Gnd Core Pwr Pad Gnd Pad Pwr I/O I/O Out
Strength
1 1 1 1 1
Reset State
Input Low Low Low Low --
Pin No.
52 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
Signal
nc FB[1] VSSIO FB[0] COL[7] COL[6] COL[5] COL[4] COL[3] COL[2] VDDIO TCLK COL[1] COL[0] BUZ D[31] D[30] D[29] D[28] VSSIO
Type
Strength
--
Reset State
In Pad Gnd In Out Out Out Out Out Out Pad Pwr In Out Out Out I/O I/O I/O I/O Pad Gnd 1 1 1 1 1 1 1 High High Low Low Low Low Low 1 1 1 1 1 1 1 1 High High High High High High
with p/u* 1 1 1 1 1
-- Low Low Low Low Input --
1 1
Low Low
Input
95 96
1
High
97 98
72 73 74 75 76 77
VDDCORE VSSIO VDDIO DRIVE[1] DRIVE[0] ADCCLK
99 100 101 1 1 1 High/ Low High/ Low Low 102 103 104
A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25]
Out I/O Out I/O Out I/O
2 1 2 1 2 1
Low Low Low Low Low Low
26
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-3. 208-Pin LQFP Numeric Pin Listing (cont.)
Pin No.
78 79 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130
Signal
ADCOUT SMPCLK VDDIO VSSIO D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] VSSIO A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] VDDIO VSSIO TNRST A[17]/ DRA[10] D[17] A[16]/ DRA[11] D[16] A[15]/ DRA[12] D[15]
Type
Out Out Pad Pwr Pad Gnd I/O Out I/O Out I/O Out I/O Pad Gnd Out I/O Out I/O Out I/O Pad Pwr Pad Gnd In Out I/O Out I/O Out
Strength
1 1
Reset State
Pin No.
105 106
Signal
HALFWORD A[24]/DRA[3] A[13] D[13] A[12] D[12] A[11] VDDIO VSSIO D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] VSSIO D[7] NBATCHG NEXTPWR BATOK NPOR NMEDCHG/ NBROM NURESET VDDOSC
Type
Out Out Out I/O Out I/O Out Pad Pwr Pad Gnd I/O Out I/O Out I/O Out I/O Out Pad Gnd I/O In In In In In In VDDOSC VSSOSC Osc Pwr 3M6864 Osc
Strength
1 1 1 1 1 1 1
Reset State
Low Low Low Low Low Low Low
-- -- 1 1 1 1 1 1 1 Low Low Low Low Low Low Low -- 1 1 1 1 1 1 Low Low Low Low Low Low -- -- -- 1 1 1 1 1 Low Low Low Low Low
134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
1 1 1 1 1 1 1 1
Low Low Low Low Low Low Low Low
1
Low
Schmitt
Schmitt --
131
I/O
1
Low
158
MOSCIN
X
DS352PP3 JUL 2001
Pin Information
27
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-3. 208-Pin LQFP Numeric Pin Listing (cont.)
Pin No.
132 133
Signal
A[14] D[14]
Type
Out I/O
Strength
1 1
Reset State
Low Low
Pin No.
159 160
Signal
MOSCOUT VSSOSC
Type
3M6864 Osc VSSOSC VSSCOR EOsc Gnd Out Out Out I/O I/O VSSIOV DDIOPad Gnd I/O I/O Out Out I/O I/O Pad Pwr Pad Gnd I/O I/O Out Out Pad Gnd Out Out
Strength
Reset State
X
161 162 163 164 165 166
WAKEUP NPWRFL A[6] D[6] A[5] D[5]
In In Out I/O Out I/O
Schmitt
Input Input
185 186 187 188 189 190
CL[1] FRM M DD[3] DD[2] VSSIO
1 1 1 1 1
Low Low Low Low Low
1 1 1 1
Low Low Low Low
167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE
Pad Pwr Pad Gnd Out I/O Out I/O Out Pad Gnd I/O Out I/O Out I/O Core Gnd VDDCO REVDD RTCCor e Pwr Pad Gnd Pad Pwr 1 1 1 1 1 Low Low Low Low Low 1 1 2 1 2 Low Low Low Low Low
191 192 193 194 195 196 197 198 199 200 201 202 203 204 205
DD[1] DD[0] NRAS[1] NRAS[0] NCAS[3] NCAS[2] VDDIO VSSIO NCAS[1] NCAS[0] NMWE NMOE VSSIO NCS[0] NCS[1]
1 1 1 1 2 2
Low Low High High High High
2 2 1 1
High High High High --
1 1
High High
182 183
VSSIO VDDIO
206 207
NCS[2] NCS[3]
Out Out
1 1
High High
28
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-3. 208-Pin LQFP Numeric Pin Listing (cont.)
Pin No.
184
Signal
C[2]
Type
Out
Strength
1
Reset State
Low
Pin No.
208
Signal
NCS[4]
Type
Out
Strength
1
Reset State
High
NOTE: `With p/u' means with internal pull-up on the pin.
DS352PP3 JUL 2001
Pin Information
29
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
2.5
JTAG Pin Ordering for 208-Pin LQFP Package
Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package
Pin No.
1 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32
Signal
NCS[5] EXPCLK WORD WRITE RUN/CLKEN EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1]/ PRDY2 PB[0]/ PRDY1 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1
Type
Out I/O Out Out I/O I/O Out In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Out Out
Position
1 3 6 8 10 13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67
Pin No.
34 35 36 37 38 39 40 41 42 43 44 45 46 47 53 54 55 56 59 60 61 62 63 65 66 67
Signal
PHDIN CTS RXD1 DCD DSR NTEST1 NTEST0 EINT3 NEINT2 NEINT1 NEXTFIQ PE[2]/CLKSEL PE[1]/ BOOTSEL1 PE[0]/ BOOTSEL0 PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]/ LEDFLSH SSICCLK SSITXFR SSITXDA SSIRXDA
Type
In In In In In In In In In In In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Out In
Position
69 70 71 72 73 74 75 76 77 78 79 80 83 86 89 92 95 98 101 104 107 110 113 116 119 121
30
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package (cont.)
Pin No.
68 69 70 75 76 77 78 79 80 82 83 84 85 86 87 88 91 92 93 94 95 96 97 99 100 101 102 103 104
Signal
SSIRXFR ADCIN NADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPLCK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25]
Type
Out In Out I/O I/O Out Out Out In In Out Out Out Out Out Out Out Out Out I/O I/O I/O I/O Out I/O Out I/O Out I/O
Position
122 125 126 128 131 134 136 138 140 141 142 144 146 148 150 152 154 156 158 160 163 166 169 172 174 177 179 182 184
Pin No.
105 106 109 110 111 112 113 114 115 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 141
Signal
HALF WORD A[24]/DRA[3] D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14] D[14] A[13] D[13] A[12] D[12] A[11] D[11]
Type
Out Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O Out I/O
Position
187 189 191 194 196 199 201 204 206 209 211 214 216 219 221 224 226 229 231 234 236 239 241 244 246 249 251 254 256
DS352PP3 JUL 2001
Pin Information
31
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 2-4. JTAG Pin Ordering for 208-Pin LQFP Package (cont.)
Pin No.
142 143 144 145 146 147 148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 171 172 173 175
Signal
A[10] D[10] A[9] D[9] A[8] D[8] A[7] D[7] NBATCHG NEXTPWR BATOK NPOR NMEDCHG/ BROM NURESET WAKEUP NPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2]
Type
Out I/O Out I/O Out I/O Out I/O In In In In In In In In Out I/O Out I/O Out I/O Out I/O Out I/O
Position
259 261 264 266 269 271 274 276 279 280 281 282 283 284 285 286 287 289 292 294 297 299 302 304 307 309
Pin No.
176 177 178 179 184 185 186 187 188 189 191 192 193 194 195 196 199 200 201 202 204 205 206 207 208
Signal
A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] NRAS[1] NRAS[0] NCAS[3] NCAS[2] NCAS[1] NCAS[0] NMWE NMOE NCS[0] NCS[1] NCS[2] NCS[3] NCS[4]
Type
Out I/O Out I/O Out Out Out Out I/O I/O I/O I/O Out Out I/O I/O I/O I/O Out Out Out Out Out Out Out
Position
312 314 317 319 322 324 326 328 330 333 336 339 342 344 346 349 352 355 358 360 362 364 366 368 370
NOTE: 1)See Table 2-1. SSI/Codec/MCP Pin Multiplexing for pin naming/functionality. 2)For each pad, the JTAG connection ordering is input, output, then enable as applicable.
32
Pin Information
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
3. FUNCTIONAL DESCRIPTION
The EP7211 device is a single-chip embedded controller designed to be used in low cost and ultralow-power applications. A hand-held personal organizer and hand-held internet browser are just two of the many potential applications of the device. The EP7211 operates at 2.5 V and up to 74 MHz using the ARM7TDMI CPU with MMU, a write buffer, and cache. The EP7211 device is designed to be backward compatible with Cirrus' CLPS7111 device. For the same functionality, this device is a drop-in upgrade -- it contains the same pinout and register arrangement, making previous software binary-compatible, and system boards requiring only voltage changes in most cases.There are other devices offered by Cirrus Logic (http://www.cirrus.com) that can be used around this chip to build a complete hand-held organizer. These include IR chipsets, still camera chipsets, audio DACs, codecs, etc. The EP7211 contains additional functionality to the CL-PS7111 device that can be accessed through various pin-muxing options. The additions are: * * * * * * * ARM720T core processor -- giving Thumb and WinCETM support and dynamically programmable core clock speeds of 18 MHz, 36 MHz, 49 MHz, and 74 MHz MCP -- Multimedia Codec Port to interface to the Philips' UCB1100 codec Increased A/D data flexibility -- data width configurable between 8 to 16 bits Increased on-chip SRAM size to 38,400 bytes; the entire display memory for a 640 x 240 x 2 bits/pixel can be contained within this on-chip SRAM Dedicated LED flasher pin running from the realtime clock (RTC) EDO DRAM support (Fast Page DRAM is only supported at 13 MHz and 18 MHz) Full JTAG boundary scan and Embedded ICE support
The core-logic functionality is built around the ARM720T processor (i.e., an ARM7TDMI 32-bit RISC CPU with a WinCE compatible MMU, a write buffer, and 8 kbytes of cache). At 74 MHz and with the on-chip four-way set-associative cache, the EP7211 delivers approximately 66 Dhrystone 2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC. The EP7211 can interface to up to two banks of DRAM. Each bank can be up to 256 Mbytes in size. The DRAM interface is programmable to be 16-bit or 32-bit wide. There are also interfaces for: * * * Two ROM/SRAM/Flash banks each up to 256 Mbytes Up to four expansion devices, each up to 256 Mbytes in size An interface to up to two Cirrus Logic CL-PS6700 PC Card controller devices to support two PC Card slots
The expansion devices could be additional ROM/SRAM/Flash as well. In addition, the EP7211 provides 38,400 bytes of on-chip SRAM that can be used for three purposes:
DS352PP3 JUL 2001
Functional Description
33
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
* * *
Critical program storage LCD frame buffer General purpose data storage
The EP7211 supports a number of serial interface protocols including two high speed (115 kbps) UARTs with RX and TX FIFOs, a codec interface with FIFO support, and two additional synchronous serial interfaces. One of the UARTs also supports the IrDA SIR protocol. The EP7211 also has an on-chip Boot ROM (128 bytes), which is hardware selectable on power-on reset. This Boot ROM initializes UART1, and downloads the application-specific main boot code into the on-chip SRAM. Once download is complete, execution jumps to the start of the on-chip SRAM. This feature could be used in a manufacturing environment to allow the EP7211 to download code into on-board blank Flash. [See Section 10 Appendix A: Boot Code on page 157] The EP7211 design is optimized for low power dissipation, and is fabricated on a fully static 0.25 micron CMOS process. It is available in 256-ball PBGA and 208-pin LQFP packages. 3.1 Main Functional Blocks The principle functional blocks in the EP7211 are: * ARM720T processor, which consists of the following functional sub-blocks:
- - - - ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) Memory management unit from the ARM700 and ARM710 processors with WinCE support; it also contains a 64-bit translation look aside buffer (TLB) 8 kbytes of unified instruction and data cache, four-way set associative cache controller Write buffer
* * * * * * * *
38,400 bytes of SRAM; full address decode is performed. Two PC Card slots supported by an interface to one CL-PS6700 per slot Interrupt controller Expansion and ROM/SRAM/Flash interface giving 4, 5, or 6 x 256 Mbyte expansion segments with independent wait states DRAM controller supporting EDO, fast page and self-refresh in the Standby State, and both 16bit and 32-bit wide memory (Fast Page DRAM is only supported at 13 MHz and 18 MHz 27 bits of general purpose peripheral I/O -- multiplexed to provide additional functionality where necessary Codec sound interface with 16-byte transmit and receive FIFOs MCP (Multimedia Codec Port) giving access to an audio codec, a telecom codec, a touchscreen interface, four general purpose analog-to-digital converter inputs, and ten programmable digital I/O lines
34
Functional Description
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
* * * * * * * * * * *
On-chip Boot ROM programmed with serial load boot sequence Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level greyscaler Programmable frame buffer start address, allowing a system to be built using only external or internal SRAM for memory, eliminating any need for DRAMs at all Two full duplex 16C550 style UARTs with two 16-byte FIFOs IrDA SIR Protocol controller capable of speeds up to 115.2 kbps Two 16-bit general purpose timer counters A 32-bit real time clock and comparator Dedicated LED flasher pin driven from the RTC with programmable duty ratio Two PWM interfaces Advanced system state control and power management Two synchronous serial interfaces for Microwire or SPI peripherals such as ADCs, one supporting both the master and slave mode and up to 512 kbps continuous data rate, while the other supports only the master mode with no buffering, and up to 128 kbps Full boundary scan -- JTAG External tracing support for debug The main oscillator and phase locked loop (PLL) to generate twice the maximum CPU clock of 73.728 MHz from a 3.6864 MHz crystal, with an alternative external clock input (used in 13 MHz mode) A low power 32.768 kHz oscillator
* * *
*
Figure 3-1. EP7211 Block Diagram shows a simplified block diagram of the EP7211. All external memory and peripheral devices are connected to the 32-bit data bus using the external 28-bit address bus and control signals. Bus transfer times can be extended using the EXPRDY signal to lengthen bus cycles.
DS352PP3 JUL 2001
Functional Description
35
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
13-MHZ INPUT 3.6864 MHZ PLL
INTERNAL DATA BUS
D0-D31
ARM720T
32.768 KHZ POR, RUN, RESET, WAKEUP BATOK, EXTPWR PWRFL, BATCHG EINT[1-3], FIQ, MEDCHG FLASHING LED DRIVE PORTS A, B, D (8-BIT) PORT E (3-BIT) KEYBD DRIVERS (0-7) BUZZER DRIVE DC-TO-DC ADCCLK, ADCIN, ADCOUT, SMPCLK, ADCCS SSICLK, SSITXFR, SSITXDA, SSIRXDA, SSIRSFR 32.768-KHZ OSCILLATOR STATE CONTROL POWER MANAGEMENT INTERRUPT CONTROLLER RTC LCD DMA GPIO PWM SSI1 (ADC) MULTIMEDIA CODEC PORT SSI2 CODEC ON-CHIP BOOT ROM TIMER COUNTERS (2) ICE-JTAG LCD CONTROLLER ON-CHIP SRAM 37.5 KBYTES UART1 UART2 8-KBYTE CACHE MMU WRITE BUFFER EXPANSION CONTROL DRAM CONTROLLER
INTERNAL ADDRESS BUS
ARM7TDMI CPU CORE
MEMORY CONTROL BLOCK CL-PS6700 INTFC.
PB[0-1], CS[4-5] EXPCLK, WORD, CS[0-3], EXPRDY, WRITE MOE, MWE, RAS[0-1], CAS[0-3] A[0-27], DRA[0-12] TEST AND DEVELOPMENT LCD DRIVE
IrDA
LED AND PHOTODIODE ASYNC INTERFACE 1 ASYNC INTERFACE 2
APB BRIDGE APB BUS
TM
Figure 3-1. EP7211 Block Diagram
3.2
CPU Core The ARM7TDMI core CPU is a 32-bit RISC processor, which is connected directly to the 8-kbyte unified cache. This cache has 512 lines of 4 words, arranged as a 4-way set associative cache. The cache is directly connected to the ARM7TDMI CPU, and therefore caches the virtual address from the CPU. The MMU translates the virtual address into a physical address, it contains a 64-entry translation look aside buffer (TLB) and is post cache; that is, it only translates external memory references (cache misses) to save power. The ARM7TDMI CPU, the MMU, the cache, and the write buffer together make up what is called the ARM720T processor. See the ARM720T Datasheet for a complete description of the various logic blocks that make up the processor, as well as all internal register information.
3.3
Interrupt Controller The ARM720T has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller in the EP7211 controls interrupts from 22 different sources. Seventeen interrupt sources are mapped to the IRQ input and five sources to the FIQ input. FIQs have a higher priority
36
Functional Description
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
than IRQs. If two interrupts within the same group (IRQ or FIQ) are active, the order in which they are serviced must be resolved in software. All interrupts are level sensitive; that is, they must conform to the following sequence. 1) The interrupting device (either external or internal) asserts the appropriate interrupt. 2) If the appropriate bit is set in the interrupt mask register, then either a FIQ or an IRQ will be asserted by the interrupt controller. (A description for each bit in this register can be found in Section 5.3.1 INTSR1 Interrupt Status Register 1 on page 94.) 3) If interrupts are enabled the processor will jump to the appropriate address. 4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the interrupt and calls the appropriate interrupt service routine(s). 5) Software in the interrupt service routine will clear the interrupt source by some action specific to the device requesting the interrupt (e.g., reading the UART RX register). The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be serviced in a similar way. Alternately, it may return to the interrupt dispatch code, which can check for any more pending interrupts and dispatch them accordingly. The "End of Interrupt" type interrupts are latched. All other interrupt sources (e.g., external interrupt source) must be held active until its respective service routine starts executing. See Section 5.13 for more details. Table 3-1, Table 3-2 and Table 3-3 show the names and allocation of interrupts in the EP7211.
Table 3-1. Interrupt Allocation in First Interrupt Register
Interrupt
FIQ FIQ FIQ FIQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ
Bit in INTMR1 and INTSR1
0 1 2 3 4 5 6 7 8 9 10 11
Name
EXTFIQ BLINT WEINT MCINT CSINT EINT1 EINT2 EINT3 TC1OI TC2OI RTCMI TINT
Comment
External fast interrupt input (NEXTFIQ pin) Battery low interrupt Watchdog expired interrupt Media changed interrupt Codec sound interrupt External interrupt input 1 (NEINT1 pin) External interrupt input 2 (NEINT2 pin) External interrupt input 3 (EINT3 pin) TC1 underflow interrupt TC2 underflow interrupt RTC compare match interrupt 64 Hz tick interrupt
DS352PP3 JUL 2001
Functional Description
37
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-1. Interrupt Allocation in First Interrupt Register (cont.)
Interrupt
IRQ IRQ IRQ IRQ
Bit in INTMR1 and INTSR1
12 13 14 15
Name
UTXINT1 URXINT1 UMSINT SSEOTI
Comment
Internal UART1 transmit FIFO empty interrupt Internal UART1 receive FIFO full interrupt Internal UART1 modem status changed interrupt Synchronous serial interface 1 end of transfer interrupt
Table 3-2. Interrupt Allocation in Second Interrupt Register
Interrupt
IRQ IRQ IRQ IRQ IRQ
Bit in INTMR2 and INTSR2
0 1 2 12 13
Name
KBDINT SS2RX SS2TX UTXINT2 URXINT2 Key press interrupt
Comment
Master/slave SSI 16 bytes received Master/slave SSI 16 bytes transmitted UART2 transmit FIFO empty interrupt UART2 receive FIFO full interrupt
Table 3-3. Interrupt Allocation in Third Interrupt Register
Interrupt
FIQ
Bit in INTMR3 and INTSR3
0
Name
MCPINT MCP interface interrupt
Comment
3.3.1 3.3.1.1
Interrupt Latencies in Different States Operating State
The ARM720T processor checks for a low level on its FIQ/IRQ inputs at the end of each instruction. First, there is a one to two clock cycle synchronization penalty. For the case where the EP7211 is operating at 13 MHz with a 16-bit external memory system, and instruction sequence stored in one wait state Flash memory, the worst case interrupt latency is 251 clock cycles. This corresponds to the processor executing a STM instruction to DRAM, and where the MMU needs to fetch protection/ translation information from page tables in DRAM memory. This includes a delay for cache line fills for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.
38
Functional Description
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
This would give a worst-case interrupt latency of about 19.3 s for the ARM720T processor operating at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is increased by the maximum time required to pass through the deglitcher, which is approximately 61 s (1 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst case latency of approximately 80 s. If the ARM720T is run at 36 MHz or greater and/or 32bit wide external memory, the 19.3 s value will be reduced. All the serial data transfer peripherals included in the EP7211 (except for the master-only SSI1) have local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This assumes that the maximum data rates described in this specification are complied with. If the OS cannot meet this requirement, there will be a risk of data over/underflow occurring. 3.3.1.2 Idle State
When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two clock cycles. However, there is still potentially up to 20 s latency as described in the first section above, unless the code is written to include at least two single cycle instructions immediately after the write to the IDLE register (in which case the latency drops to a few microseconds). This is important, as normally the Idle State will have been left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced. 3.3.1.3 Standby State
In the Standby State, the latency will depend on whether the system clock is shut down and if the FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the FASTWAKE bit is cleared, then there will be a latency of between 0.125 s to 0.25 s. If the FASTWAKE bit is set, then there will be a latency of between 250 s to 500 s. If the system is running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the latency will also be between 0.125 s and 0.25 s to enable an external oscillator to stabilize. In the case of a 13 MHz system where the clock is not disabled during the Standby State (CLKENSL = 1), then the latency will be the same as described in the Idle State section above. Whenever the EP7211 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are power-down from draining current. Also, the internal peripheral's signals get set to their Reset State.
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Table 3-4 summarizes the three external interrupt sources and the effect they have on interrupt pins.
Table 3-4. External Interrupt Source Latencies
Interrupt Pin
NEXTFIQ
Input State
Not deglitched; must be active for 20 s to be detected
Operating State Latency
Worst case latency of 20 s
Idle State Latency
Worst case 20 s: if only single cycle instructions, less than 1 s As above
Standby State Latency
Including PLL/osc. settling time, approx. 0.25 s when FASTWAKE = 0, or approx. 500 s when FASTWAKE = 1, or = Idle State if in 13 MHz mode with CLENSL set As above
NEINT1-2
Not deglitched
Worst case latency of 20 s Worst case latency of 20 s Worst case latency of 80 s
EINT3
Not deglitched
As above
As above
MEDCHG
Deglitched by 16 kHz clock; must be active for at least 80 s to be detected
Worst case 80 s: if only single cycle instructions, 61 s
As above (note difference if in 13 MHz mode with CLKENSL set)
For the case of the keyboard interrupt, the following options are available and are selectable according to bits 1 and 3 of the SYSCON2 register (refer to SYSCON2 register description for details). * If the KBWEN bit (SYSCON2 Bit 3) is set low, then a keypress will cause a transition from a power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is high). When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the "Keyboard Direct Wakeup' mode. In this mode, the interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt. When the KBD6 bit (SYSCON2 Bit 1) is low, all 8 of Port A inputs are OR'ed together to produce the internal wakeup signal and keyboard interrupt request. This is the default reset state. When the KBD6 bit (SYSCON2 Bit 1) is high, only the lowest 6 bits of Port A are OR'ed together to produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of Port A are available as GPIO when this bit is set high.
*
*
*
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In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup the device by using the external WAKEUP pin or another enabled interrupt source. The keyboard interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a combination of both.
NOTE: The keyboard interrupt is NOT deglitched.
3.4
Memory and I/O Expansion Interface Six separate linear memory or expansion segments are decoded by the EP7211, two of which can be reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the SRAM space is fully decoded up to the maximum size of the video frame buffer programmed in the LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded (i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of the six segments can be configured to interface to a conventional SRAM-like interface, and can be individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute from 1 to 4 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait state sequential access feature is designed to support burst mode ROMs. For writeable memory devices which use the NMWE pin, zero wait state sequential accesses are not permitted and one wait state is the minimum which should be programmed in the sequential field of the appropriate MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal. Page mode access is accomplished by setting SQAEN = 1, which enables accesses of the form one random address followed by three sequential addresses, etc., while keeping NCS asserted. These sequential bursts can be up to four words long before NCS is released to allow DMA and refreshes to take place. This can significantly improve bus bandwidth to devices such as ROMs which support page mode. When SQAEN = 0, all accesses to the ROM/SRAM/Flash are by random access without NCS being de-asserted between accesses. Again NCS is de-asserted after four consecutive accesses to allow refreshes, etc. Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (NCS4 and/or NCS5) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 Bit 5 determines the function of chip select NCS4 (i.e., CL-PS6700 interface or standard chip select functionality); Bit 6 controls NCS5 in a similar way. There is no interaction between these bits. For applications that require a display buffer smaller than 38,400 bytes, the on-chip SRAM can be used as the frame buffer and no external DRAM needs to be used. The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on reset. These inputs are latched by the rising edge of NPOR to select the boot option.
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Table 3-5. Boot Options
PE[1]
0 0 1 1
PE[0]
0 1 0 1
Boot Block(NCS0)
32-bit 8-bit 16-bit Undefined
3.5
EP7211 Boot ROM The 128 bytes of on-chip Boot ROM contain a instruction sequence that initializes the device and then configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip SRAM. Once the download is complete, execution jumps to the start of the on-chip SRAM. This would allow, for example, code to be downloaded to program system Flash during a product's manufacturing process. See Section 10 Appendix A: Boot Code on page 157 for details of the ROM Boot Code with comments to describe the stages of execution. Selection of the Boot ROM option is determined by the state of the NMEDCHG pin during a power on reset. If NMEDCHG is high while NPOR is active, then the EP7211 will boot from an external memory device connected to CS0 (normal boot mode). If NMEDCHG is low, then the boot will be from the on-chip ROM. Note that in both cases, following the de-assertion of power on reset, the EP7211 will be in the Standby State and requires a low-to-high transition on the external WAKEUP pin in order to actually start the boot sequence. The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects internally. Table 3-6 shows this decoding. The control signal for the boot option is latched by NPOR, which means that the remapping of addresses and bus widths will continue to apply until NPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be read back from address 0x00000000 onwards, and in normal state of operation the Boot ROM contents can be read back from address range 0x70000000.
Table 3-6. Chip Select Address Ranges After Boot From On-Chip Boot ROM
Address Range
0000.0000-0FFF.FFFF 1000.0000-1FFF.FFFF 2000.0000-2FFF.FFFF 3000.0000-3FFF.FFFF 4000.0000-4FFF.FFFF
Chip Select
CS7 (Internal only) CS6 (Internal only) NCS5 NCS4 NCS3
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Table 3-6. Chip Select Address Ranges After Boot From On-Chip Boot ROM (cont.)
Address Range
5000.0000-5FFF.FFFF 6000.0000-6FFF.FFFF 7000.0000-7FFF.FFFF NCS2 NCS1 NCS0
Chip Select
3.6
CL-PS6700 PC Card Controller Interface Two of the expansion memory areas are dedicated to supporting up to two CL-PS6700 PC Card controller devices. These are selected by NCS4 and NCS5 (once enabled by bits 5 and 6 of SYSCON2). For efficient, low power operation, both address and data are carried on the lower 16 bits of the EP7211 data bus. Accesses are initiated by a write or read to or from the area of memory allocated for NCS4 or NCS5. The memory map within each of these areas is segmented to allow different types of PC Card accesses to take place, for attribute, I/O, and common memory space. The CL-PS6700 internal registers are memory mapped within the address space as shown in Table 3-7. CL-PS6700 Memory Map.
NOTE: It must be noted that, due to the operating speed of the CL-PS6700, this interface is supported only for processor speeds of 13 and 18 MHz.
Table 3-7. CL-PS6700 Memory Map
Access Type
Attribute I/O Common memory CL-PS6700 registers
Addresses for CL-PS6700 Interface 1
0x40000000-0x43FFFFFF 0x44000000-0x47FFFFFF 0x48000000-0x4BFFFFFF 0x4C000000-0x4FFFFFFF
Addresses for CL-PS6700 Interface 2
0x50000000- 0x53FFFFFF 0x54000000-0x57FFFFFF 0x58000000-0x5BFFFFFF 0x5C000000-0x5FFFFFFF
A complete description of the protocol and AC timing characteristics can be found in the CL-PS6700 Databook. A transaction is initiated by an access to the NCS4 or NCS5 area. The chip select is asserted, and on the first clock, the upper 10 bits of the PC Card address, along with 6 bits of size, space, and slot information are put out onto the lower 16 bits of the EP7211's data bus. Only word (i.e., 4-byte) and single-byte accesses are supported, and the slot field is hardcoded to 11, since the slot field is defined as a `Reserved field' by the CL-PS6700. The chip selects are used to select the device to be accessed. The space field is made directly from the A26 and A27 CPU address bits, according to the decode shown in Table 3-8. Space Field Decoding below. The size field is forced to 11 if a word access is required, or 00 if a byte access is required. This avoids the need to configure the interface after a reset. On the second clock cycle, the remaining 16 bits of the PC Card address are multiplexed out onto the lower 16 bits of the data bus. If the transaction selected is a CL-PS6700 register transaction, or a write to the PC Card (assuming there is space available in the CL-PS6700's
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internal write buffer) then the access will continue on the following two clock cycles. During these following two clock cycles the upper and lower halves of the word to be read or written will be put onto the lower 16 bits of the main data bus.
Table 3-8. Space Field Decoding
Space Field Value
00 01 10 11
PC CARD Memory Space
Attribute I/O Common memory CL-PS6700 registers
The `ptype' signal on the CL-PS6700s should be connected to the EP7211's WRITE output pin. During PC Card accesses, the polarity of this pin changes and it becomes low to signify a write and high to signify a read. It is valid with the first half word of the address. During the second half word of the address it is always forced high to indicate to the CL-PS6700 that the EP7211 has initiated either the write or read. The PRDY signals from each of the two CL-PS6700 devices are connected to Port B bits 0 and 1, respectively. When the PC CARD1 or PC CARD2 control bits in the SYSCON2 register are deasserted, these port bits are available for GPIO. When asserted, these port bits are used as the PRDY signals. When the PRDY signal is de-asserted (i.e., low), it indicates that the CL-PS6700 is busy accessing its card. If a PC CARD access is attempted while the device is busy, the PRDY signal will cause the EP7211's CPU to be stalled. The EP7211's CPU will have to wait for the card to become available. DMA transfers to the LCD can still continue in the background during this period of time (as described below). The EP7211 can access the registers in the CL-PS6700, regardless of the state of the PRDY signal. If the EP7211 needs to access the PC CARD via the CL-PS6700, it waits until the PRDY signal is high before initiating a transfer request. Once a request is sent, the PRDY signal indicates if data is available. In the case of a PC Card write, writes can be posted to the CL-PS6700 device, with the same timing as CL-PS6700 internal register writes. Writes will normally be completed by the CL-PS6700 device independent of the EP7211 processor activity. If a posted write times out, or fails to complete for any other reason, then the CL-PS6700 will issue an interrupt (i.e., a WR_FAIL interrupt). In the case where the CL-PS6700 write buffer is already full, the PRDY signal will be de-asserted (i.e., driven low) and the transaction will be stalled pending an available slot in the buffer. In this case, the EP7211's CPU will be stalled until the write can be posted successfully. While the PRDY signal is de-asserted, the chip select to the CL-PS6700 will be de-asserted and the main bus will be released so that DMA transfers to the LCD controller can continue in the background. In the case of a PC Card read, the PRDY signal from the CL-PS6700 will be de-asserted until the read data is ready. At this point, it will be reasserted and the access will be completed in the same way as for a register access. In the case of a byte access, only one 16-bit data transfer will be required to complete the access. While the PRDY signal is de-asserted, the chip select to the CL-PS6700 will 44
Functional Description DS352PP3 JUL 2001
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
be de-asserted and the main bus will be released so that DMA transfers to the LCD controller can continue in the background. The EP7211 will re-arbitrate for control of the bus when the PRDY signal is reasserted to indicate that the read or write transaction can be completed. The CPU will always be stalled until the PC Card access is completed. A card read operation may be split into a request cycle and a data cycle, or it may be combined into a single request/data transfer cycle. This depends on whether the data requested from the card is available in the prefetch buffer (internal to the CL-PS6700). The request portion of the cycle, for a card read, is similar to the request phase for a card write (described above). If the requested data is available in the prefetch buffer, the CL-PS6700 asserts the PRDY signal before the rising edge of the third clock and the EP7211 continues the cycle to read the data. Otherwise, the PRDY signal is de-asserted and the request cycle is stalled. The EP7211 may then allow the DMA address generator to gain control of the bus, to allow LCD refreshes to continue. When the CL-PS6700 is ready with the data, it asserts the PRDY signal. The EP7211 then arbitrates for the bus and, once the request is granted, the suspended read cycle is resumed. The EP7211 resumes the cycle by asserting the appropriate chip select, and data is transferred on the next two clocks if a word read (one clock if a byte read). There is no support within the EP7211 for detecting time-outs. The CL-PS6700 device must be programmed to force the cycle to be completed (with invalid data for a read) and generate an interrupt if a read or write access is timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system software can then determine which access was not successfully completed by reading status registers within the CL-PS6700. The CL-PS6700 has support for DMA data transfers. However, DMA is supported only by software emulation because the DMA address generator built into the EP7211 is dedicated to the LCD controller interface. If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to make a DMA request. This can be connected to one of the EP7211's external interrupts and be used to interrupt the CPU so that the software can service the DMA request under program control. Each of the CL-PS6700 devices can generate an interrupt PIRQ. The PIRQ output is open drain on the CL-PS6700 devices, so if there are two CL-PS6700 devices they may be wire OR'ed to the same interrupt which can be connected to one of the EP7211's active low external interrupt sources. On the receipt of an interrupt, the CPU can read the interrupt status registers on the CL-PS6700 devices to determine the cause of the interrupt. All transactions are synchronized to the EXPCLK output from the EP7211 in 18.432 MHz mode or the external 13 MHz clock. The EXPCLK should be permanently enabled, by setting the EXCKEN bit in the SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card interface and CL-PS6700 internal write buffers need to be clocked after the EP7211 has completed its bus cycles. A GPIO signal from the EP7211 can be connected to the PSLEEP pin of the CL-PS6700 devices to allow them to be put into a power saving state before the EP7211 enters the Standby State. It is
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essential that the software monitor the appropriate status registers within the CL-PS6700s to ensure that there are no pending posted bus transactions before the Standby State is entered. Failure to do this will result in incomplete PC Card accesses. 3.7 DRAM Controller with EDO Support The DRAM controller in the EP7211 provides all the connections to directly interface to up to two banks of (EDO) DRAM, and the width of the memory interface is programmable to 16-bit or 32-bit. Both banks have to be of the same width. The 16/32-bit DRAM width selection is made based on Bit 2 of the SYSCON2 register. Each of the two banks supported can be up to 256 Mbytes in size. Two RAS lines and four CAS lines are provided, with one CAS line per byte lane. The DRAM controller does not support device size programmability. Therefore, if two banks are implemented and DRAM devices are used that would create a bank smaller than 256 Mbytes, then this would lead to a segmented memory map. Each segmented bank will be separated by 256 Mbytes. Segments that are smaller than the bank size will repeat within the bank. Table 3-9. Physical to DRAM Address Mapping shows the mapping of the physical address to DRAM row and column addresses. This mapping has been organized to support any DRAM device size from 4 Mbit to 1 Gbit with a square row and column configuration (i.e., the number of column addresses is equal to the number of row addresses). If a non-square DRAM is used, further fragmentation of the memory map will occur, however the smallest contiguous segment will always be 1 Mbyte. With proper mapping of pages/sections by the MMU, one can create contiguous memory blocks. On boot-up, the DRAM controller is configured for operation with an 18.432 MHz internal bus speed, and therefore, can support either fast page mode or EDO DRAM. In this case, the read data from the DRAM is latched within the EP7211 during the high phase of the NCAS output strobes. The DRAM must not have an access time greater than 70 ns in order to meet the 18 MHz timing requirements. When the internal bus is operating at 36.864 MHz (i.e., for CPU clock frequencies of 36.864, 49.152, or 73.728 MHz), the DRAM controller will only operate with EDO DRAM. When operating at 36 MHz, the EDO DRAM must not have an access time greater than 50 ns. The DRAM cycle timings are adjusted to take advantage of the additional performance available from fast EDO DRAM. In EDO mode, the EP7211 design relies on the DRAM data being driven to be available on the external data bus during the entire high phase of the NCAS signal so that it can be latched towards the end of the cycle. In Fast Page mode, the data should be latched at the rising edge of NCAS. It is not possible to use the EP7211 with fast page mode DRAM at operating frequencies of 36 MHz or higher. The DRAM controller breaks all sequential access, so that the minimum page sizes defined can be supported. All of the possible page sizes are multiples of the minimum page size, so by breaking up accesses on minimum page sizes by default, all accesses crossing larger page boundaries are broken up.
NOTE: This bit will be generated by the DRAM controller.
An example of the DRAM connections for a typical system can be found in Figure 3-13. A Maximum EP7211 Based System. 46
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 3-9. Physical to DRAM Address Mapping
DRAM Address Pins
0 1 2 3 4 5 6 7 8 9 10 11 12
DRAM Column x16 Mode
A1* A2 A3 A4 A5 A6 A7 A8 A18 A20 A22 A24 A26
DRAM Column x32 Mode
A2 A3 A4 A5 A6 A7 A8 A9 A19 A21 A23 A25 A27
DRAM Row x16 Mode
A9 A10 A11 A12 A13 A14 A15 A16 A17 A19 A21 A23 A25
DRAM Row x32 Mode
A10 A11 A12 A13 A14 A15 A16 A17 A18 A20 A22 A24 A26
7211 Pin Name
A[27]/DRA[0] A[26]/DRA[1] A[25]/DRA[2] A[24]/DRA[3] A[23]/DRA[4] A[22]/DRA[5] A[21]/DRA[6] A[20]/DRA[7] A[19]/DRA[8] A[18]/DRA[9] A[17]/DRA[10] A[16]/DRA[11] A[15]/DRA[12]
Table 3-10 and Table 3-11. DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System show the address mapping for various DRAM's with square and non-square row and address inputs assuming two x16 devices are connected to each RAS line with 32-bit wide DRAM operation selected. This mapping is then repeated every 256 Mbytes for each DRAM bank. The placeholder `n' below is equal to 0xC + bank number (e.g., 0xC for bank 0, 0xD for bank 1).
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Table 3-10. DRAM Address Mapping When Connected to an External 32-Bit DRAM Memory System
EP7211 Size
4 Mbit 16 Mbit 16 Mbit
Address Configuration
9 Row x 9 Column 10 Row x 10 Column 12 Row x 8 Column
Total Size of Bank
1 Mbyte 4 Mbytes 4 Mbytes
Address Range of Segment(s)
n000.0000-n00F.FFFF n000.0000-n03F.FFFF n000.0000-n007.FFFF n010.0000-n017.FFFF n040.0000-n047.FFFF n050.0000-n057.FFFF n100.0000-n107.FFFF n110.0000-n117.FFFF n140.0000-n147.FFFF n150.0000-n157.FFFF n000.0000-n0FF.FFFF n000.0000-n01F.FFFF n040.0000-n05F.FFFF n100.0000-n11F.FFFF n140.0000-n15F.FFFF n400.0000-n41F.FFFF n440.0000-n45F.FFFF n500.0000-n51F.FFFF n540.0000-n55F.FFFF n000.0000-n3FF.FFFF n000.0000-nFFF.FFFF
Size of Segment(s)
1 MByte 4 Mbytes 512 KBytes 512 KBytes 512 KBytes 512 KBytes 512 KBytes 512 KBytes 512 KBytes 512 KBytes 16 Mbytes 2 MByte 2 MByte 2 MByte 2 MByte 2 MByte 2 MByte 2 MByte 2 MByte 64 Mbytes 256 Mbytes
64 Mbit 64 Mbit
11 Row x 11 Column 13 Row x 9 Column
16 Mbytes 16 Mbytes
256 Mbit 1 Gbit
12 Row x 12 Column 13 Row x 13 Column
64 Mbytes 256 Mbytes
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Table 3-11. DRAM Address Mapping for a 16-Bit-Wide DRAM Memory System
EP7211 Size
4 Mbit 16 Mbit 16 Mbit
Address Configuration
9 Row x 9 Column 10 Row x 10 Column 12 Row x 8 Column
Total Size of Bank
0.5 Mbyte 2 Mbytes 2 Mbytes
Address Range of Segment(s)
n000.0000-n007.FFFF n000.0000-n01F.FFFF n000.0000-n003.FFFF n008.0000-n00B.FFFF n020.0000-n023.FFFF n028.0000-n02B.FFFF n080.0000-n083.FFFF n088.0000-n08B.FFFF n0A0.0000-n0A3.FFFF n0A8.0000-n0AB.FFFF n000.0000-n07F.FFFF n000.0000-n00F.FFFF n020.0000-n02F.FFFF n080.0000-n08F.FFFF n0A0.0000-n0AF.FFFF n200.0000-n20F.FFFF n220.0000-n22F.FFFF n280.0000-n28F.FFFF n2A0.0000-n2AF.FFFF n000.0000-n1FF.FFFF n000.0000-n7FF.FFFF
Size of Segment(s)
0.5 MByte 2 Mbytes 256 KBytes 256 KBytes 256 KBytes 256 KBytes 256 KBytes 256 KBytes 256 KBytes 256 KBytes 8 Mbytes 1 MByte 1 MByte 1 MByte 1 MByte 1 MByte 1 MByte 1 MByte 1 MByte 32 Mbytes 128 Mbytes
64 Mbit 64 Mbit
11 Row x 11 Column 13 Row x 9 Column
8 Mbytes 8 Mbytes
256 Mbit 1 Gbit
12 Row x 12 Column 13 Row x 13 Column
32 Mbytes 128 Mbytes
The DRAM controller contains a programmable refresh counter. The refresh rate is controlled using the DRAM refresh period register (DRFPR). The 16/32-bit DRAM selection is made based on Bit 2 of the SYSCON2 register. Both banks must have the same width. SYSCON2 0x8000 1100 Bit 2 (DRAMSZ)0 = 32-bit DRAM 1 = 16-bit DRAM The default is 32-bit width, since the SYSCON2 register is reset to all zeros on power-up.
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3.8
Serial Interfaces The EP7211 offers the following serial interfaces in addition to the two UARTs.
Table 3-12. Serial Interface Options
Type Comments
Master mode only Master/slave mode Touchscreen, codecs, and GPIO Only for use in the PLL clock mode
Referred To As
ADC Interface SSI2 Interface MCP Interface Codec Interface
Max. Transfer Speed
128 Kbps 512 Kbps 9.216 Mbps 64 Kbps
SPI/Microwire 1 SPI/Microwire 2 MCP Interface Codec Interface
The inputs/outputs of three of the serial synchronous interfaces (MCP, codec, and SSI2) are multiplexed onto a single set of external interface pins. If the MCPSEL bit of SYSCON3 is low, then either SSI2 or the codec interface will be selected to connect to the external pins. When Bit 0 of SYSCON2 (SERSEL) is high, then the codec is connected to the external pins, when low the master/slave SSI2 is connected to these pins. When the MCPSEL bit is set high, the MCP interface is connected to the external pins. On power up, both the MCPSEL and SERSEL bits are reset low, thus the master/slave SSI2 will be connected to these pins (and configured for slave mode operation to avoid external drive clashes). The following table contains pin definition information for the three multiplexed interfaces.
NOTE: The internal names given to each of the three interfaces are unique to help differentiate them from each other. The sections below that describe each of the three interfaces will use their respective unique internal pin names for clarity.
Table 3-13. Serial-Pin Assignments
Pin No. LQFP
63 65 66 67 68
External Pin Name
SSICCLK SSITXFR SSITXDA SSIRXDA SSIRXFR
SSI2 Slave Mode (Internal Name)
SSICCLK = serial bit clock; Input SSKTXFR = TX frame sync; Input SSITXDA = TX data; Output SSIRXDA = RX data; Input SSIRXFR = RX frame sync; Input
SSI2 Master Mode
Output Output Output Input Output
Codec Internal Name
PCMCLK = Output PCMSYNC = Output PCMOUT = Output PCMIN = Input p/u*
MCP Internal Name
SIBCLK = Output SIBSYNC = Output SIBDOUT = Output SIBDIN = Input p/u*
Strength
1 1 1
1
* p/u = use an 10 k pull-up
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3.8.1
Codec Sound Interface
The codec interface allows direct connection of a telephony type codec to the EP7211. It provides all the necessary clocks and timing pulses and performs a parallel to serial conversion or vice versa on the data stream to or from the external codec device. The interface is full duplex and contains two separate data FIFOs (16 deep by 8-bits wide, one for the receive data, another for the transmit data). Data is transferred to or from the codec at 64 kbps. The data is either written to or read from the appropriate 16 byte FIFO. If enabled, a codec interrupt (CSINT) will be generated after every 8 bytes are transferred (FIFO half full/empty). This means the interrupt rate will be every 1 ms, with a latency of 1 ms. Transmit and receive modes are enabled by asserting high both the CDENRX and CDENTX codec enable bits in the SYSCON1 register.
NOTE: Both the CDENRX and CDENTX enable bits should be asserted in tandem for data to be transmitted or received. The reason for this is that the interrupt generation will occur 1 ms after one of the FIFOs is enabled. For example: If the receive FIFO gets enabled first and the transmit FIFO at a later time, the interrupt will occur 1 ms after the receive FIFO is enabled. After the first interrupt occurs, the receive FIFO will be half full. However, it will not be possible to know how full the transmit FIFO will be since it was enabled at a later time. Thus, it is possible to unintentionally overwrite data already in the transmit FIFO. See the following diagram:
CDENRX CDENTX CSINT
1 ms Interrupt occurs
1 ms Interrupt occurs
1 ms Interrupt occurs
Figure 3-2. Codec Interrupt Timing
3.8.1.1
Codec Interrupt Timing
After the CDENRX and CDENTX enable bits get asserted, the corresponding FIFOs become enabled. When deasserted low, the FIFO status flags (i.e., CRXFE and CTXFF located in the SYSFLAG register) are cleared and the FIFOs appear empty. Additionally, if the CDENTX bit is low, the PCMOUT output is disabled. Asserting either of the two enable bits causes the sync and interrupt generation logic to become active; otherwise they are disabled to conserve power.
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Data is loaded into the transmit FIFO by writing to the CODR register. At the beginning of a transmit cycle, this data is loaded into a shift/load register. Just prior to the byte being transferred out, PCMSYNC goes high for one PCMCLK cycle. Then the data is shifted out serially to PCMOUT, MSB first, (with the MSB valid at the same time PCMSYNC is asserted). Data is shifted on the rising edge of the PCMCLK output. Receiving of data is performed by taking data in serially through PCMIN, again MSB first, shifting it through the shift/load register and loading the complete byte into the receive FIFO. Input data is sampled on the falling edge of PCMCLK. Data is read from the CODR register.
NOTE: After data is transmitted, the speaker amplifier should be turned off to avoid audible noise. This is needed because the EP7211 will continue to transmit data from the FIFO even though it is empty, thus causing noise. This will occur even when receiving.
3.8.2
MCP Interface
The Multimedia Communications Port (MCP) provides an interface to the Philips UCB1100 codec. This device has an audio codec, a telecom codec, a touch-screen interface, four general purpose ADC inputs, and ten programmable digital I/O lines. The MCP interface is used by the device both to input and output digital data to and from the codec, and to configure and acquire status information from the codec's 16 registers. The MCP produces two 64-bit subframes per frame (128 bits for both subframes in the frame) using a bit clock and frame synchronization signal. Data is communicated full duplex via a separate transmit and receive data line. The bit clock frequency is fixed at 9.216 Mbps for all modes except the 13 MHz mode. For the 13 MHz mode, the bit clock frequency is fixed at 6.5 Mbps. The MCP communicates to the codec in the first of the two subframes. The second subframe is used in highend applications to communicate with a second stereo codec, such as Crystal's CS4216/18, however this feature is not supported by the MCP. Each 64-bit subframe contains seven different fields of information. These fields include audio conversion data, telecom conversion data, data valid flags, control register address, control register data, and read/write control. Both transmit and receive data contains these seven fields. The transmitted frame contains data for D-to-A conversion, as well as address, data, and control signals to write to or read from the codec's registers. The received frame contains A-to-D samples, and the data returned from a read of a codec register. Both the MCP and the off-chip codec contain programmable 7-bit divisors, one each for the telecom and audio data. These values are used to divide the bit clock to generate a desired sampling frequency. When the codec is enabled, the divisor pairs are synchronously transferred to their respective modulus registers within the MCP and codec' and decrement using the bit clock. This technique allows telecom and audio data to be transferred between the MPC and codec, lock-step in sync with the sampling/conversion frequency of the codec. The MCP contains two pairs of transmit FIFOs and two pairs of receive FIFOs, one each for audio and telecom data. In the current implementation, the two receive FIFOs are deeper than the two transmit FIFOs. The sizes of the audio/telecom transmit FIFOs are 8 x 16-bit words and of the audio/telecom receive FIFOs are 12 x 16-bit words. The MCP also contains a 21-bit data register used to transmit codec register reads and writes, as well as another 21-bit register to receive the results of 52
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codec register reads. Touch-screen and ADC conversions are triggered, and the digital I/O lines are controlled using codec register writes, while the converted data and the state of digital I/O lines is accessed using a codec register read. 3.8.2.1 MCP Operation
Following reset, the MCP logic is disabled. To enable the MCP the applications program should first clear the emergency underflow and overflow status bits, which are set following the reset, by writing a 1 to these register bits (during a MCSR read access). Next, the user should program the MCP control register with the desired mode of operation using a word write. The user may choose to either "prime" the audio and telecom transmit FIFOs by writing up to eight 16-bit values each, or allow the FIFO service requests to interrupt the CPU and trigger an EPB transfer to fill the FIFOs. Once the off-chip codec is programmed and data resides within the bottom entries of the audio and/or telecom FIFOs, transmission/reception of data begins on the transmit (SIBDOUT) and receive (SIBDIN) pins. This is synchronously controlled by the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock (SIBCLK) and serial frame (SIBSYNC) pins. 3.8.2.2 MCP Frame Format
Each MCP data frame is 128 bits long and is divided into two subframes: 0 and 1. Subframe 0 is used by the MCP to communicate data to and from the UCB1100. Subframe 1 is not used by the MCP, since it is typically used to interface to high-performance stereo codecs like Crystal's CS4216/18. After the MCP is enabled, SIBCLK begins to transition at a fixed rate of 9.216 MHz (6.5 MHz in the 13 MHz mode) and the start of the first frame is signalled by driving the SIBSYNC pin high for one SIBCLK period. The rising-edge of SIBSYNC coincides with the rising-edge of SIBCLK, one clock cycle immediately before each frame start. The SIBSYNC pulse causes the MCP to transfer any available audio and/or telecom data from their respective transmit FIFOs to a 64-bit serial shifter, setting the appropriate audio/telecom valid flags as well. If the codec control register contains valid data, the register value and address is placed within the appropriate fields within the shifter, and the read/write bit is configured to indicate which type of register access is to be made. For any field that does not have valid data available, the previous value transmitted is used. As long as the MCP is enabled, data frames are continuously transferred, even if valid data may not be available for transmission. The format of data transmitted and received in subframe 0 is shown in Figure 3-3. Data Format of MCP Subframe 0. Note that the UCB1100 data sheet uses Big Endian notation to specify the MCP frame bit positions; however, Little Endian notation is used here to remain consistent with the rest of the device specification.
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Bit TX
63
48
47 0
46 Address
43
42 R/ W
41 00000000
34
33 AV
32 T V
31
16
15 Control Register Write
0
Audio Transmit Data
Telecom Transmit Data
RX
Audio Receive Data
0
Address
R/ W
00000000
AV
T V
Telecom Receive Data
Control Register Read
NOTE: AV - Audio Data Valid, TV - Telecom Data Valid, R/W - write=1 read=0, Address -- codec register address
Figure 3-3. Data Format of MCP Subframe 0
Both the MCP and the off-chip codec drive data on the rising-edge of SIBCLK and latch data on its falling-edge. After SIBSYNC is negated, subframe 0 begins and the data within the 64-bit shifter is driven onto the SIBDOUT pin a bit at a time, starting with MSB[63]. As each bit of data is shifted onto the SIBDOUT pin from one side of the shifter, a bit is also shifted into the opposite end of the shifter from the SIBDIN pin. After 64 SIBCLK cycles elapse, all data within the shifter has been transmitted, and the shifter contains the 64-bit receive data frame. The MCP takes the data from each field and places it in its respective receive FIFO or data register. The next 64 SIBCLK cycles make up subframe 1. When subframe 1 is active, the clocks to all MCP resources, which are not needed, are turned off in order to conserve power. Table 3-4 shows the pin timing of the MCP.
Frame Clock Count 1 Frame N Subframe SIBCLK Subframe 0 ... Subframe 1 ... 2 ... 63 64 65 66 ... 127 128 1 Frame N+1
SIBSYNC
...
SIBDOUT
[63]
[62]
...
[1]
[0]
[63]
...
[0]
[63]
SIBDIN
[63]
[62]
...
[1]
Bit
[63]
...
[0]
[63]
Figure 3-4. MCP Packet Organization
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Note that the transmit line is pulled low any time data is not being driven onto the pin. The UCB1100 has a programming option which allows it to either tristate or drive the receive line low when data is not driven onto SIBDIN. As shown in Figure 3-4, the MCP frames occur back-to-back. The SIBSYNC pin is driven high during the last clock (128th) of the frame to indicate the start of a new frame the following SIBCLK period. Values contained within the transmit FIFOs are loaded to the shift register on the rising-edge of SIBSYNC. 3.8.2.3 Audio and Telecom Sample Rates and Data Transfer
The UCB1100 contains an audio and telecom codec with sample rates that can be individually programmed, and are derived from the 9.216 MHz (6.5 MHz in 13 MHz mode) serial clock (SIBCLK), which is supplied by the MCP interface. This is derived originally from the divided chip clock. For the UCB1100 audio codec, with an input clock as above, valid sample rates are derived by dividing the serial clock first by a fixed value of 32 and then by a value from 9 to 127. For the UCB1100 telecom codec, the sample rate is derived by dividing the serial clock first by a fixed value of 32 and then by a value from 16 to 127. Nominal sample frequencies are 7.2 kHz for the telecom codec and 22.05 kHz for the audio codec. For a SIBCLK of 9.216 MHz, the sample rate of the telecom codec using a divisor of 40, is exactly correct while for the audio codec, using a divisor of 13, the sample rate error is less than +0.5%. For a SIBCLK of 6.5 MHz, the sample rate error of the telecom codec using a divisor of 28, is less than +0.75%, while for the audio codec using a divisor of 9 the sample rate error is less than +2.5%. The codec and the MCP both contain an audio and a telecom sample rate counter. These counters are used to achieve conversion rate synchronization between the codec and the MCP, so that data may be coherently transferred between the MCP and the codec. For the remainder of this description all references are made to the audio codec for brevity; however, all information also applies to the telecom portion of the codec and the MCP. Before enabling the audio codec, the audio sample rate counters within the codec and the MCP must be programmed with the same divisor value so that they have the same clock rate. The codec's audio sample rate divisor is programmed by issuing a control register write transfer and the MCP's divisor is programmed using the CPU by writing to the MCP's control register. Both the MCP and the codec's audio counters are reloaded with the programmed modulus value any time the audio portion of the codec is enabled. This can also be accomplished by performing a control register write transfer or whenever the sample rate counters reach zero. The MCP and the audio codec decrement their counters in lock-step with one another, both starting on the occurrence of the first SIBSYNC pulse after the audio codec is enabled. Samples/conversions are made each time the audio codec's counter reaches zero. Figure 3-5 shows the timing of the audio codec enable, as well as decrements of the MCP and audio codec's sample counter.
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Subframe SIBSYNC
01
01
01
01
01
01
01
01
01
01
01
SIBDOUT
Ena
Dis
Audio Ena
Counters
3
3
2
1
3
2
1
3
2
3...................3
Samp/Conv
Figure 3-5. Audio Codec Enable Timing
Referring to the Figure 3-5. Audio Codec Enable Timing, "Ena" within the data frame on SIBDOUT represents a control register write to the codec to enable the input portion of the audio codec. The register is updated with the write at the end of subframe 0, and the audio enable signal within the codec goes high. Both the MCP and codec's audio sample rate counters then start to decrement on the next SIBSYNC pulse. In the example, a divisor value of 3 is used, causing the counter to decrement to zero after 96 (32 x 3 = 96) SIBCLK cycles occur. If the input portion of the audio codec is enabled when the counter reaches zero, a sample and A/D conversion is made. The converted value is then placed into the correct field of the codec's serial shift register for transmission back to the MCP in the next data frame. If the output portion of the audio codec is enabled, an audio data value is taken from the received data supplied by the MCP and is used for a D/A conversion. Data used in the D/A conversion is always taken from the previous MCP input frame. If no new data is available within the MCP's audio transmit FIFO since the last D/A conversion, the same data is used again (causing audio distortion). Samples and conversions occur twice as shown in Figure 3-5. Audio Codec Enable Timing. However, while the counter is decrementing for the third time, the CPU disables the audio codec by issuing another control register write, represented by the "Dis" data frame on SIBDOUT. The SIBSYNC pulse following the write causes the disable to take effect, and the MCP and codec's audio sample rate counters are stopped and reset to their modulus value. The MCP and the codec's audio sample rate counters must be enabled coherently, so that synchronization is achieved between the two. This is accomplished by first programming both the MCP and codec's sample rate modulus values, then performing a codec control register write to enable the audio sampling rate counter within the codec. The MCP automatically decodes a write to
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the audio codec input and output enable bits and enables the MCP's audio sample rate counter at the same time as the codec's counter to ensure synchronization. The UCB1100 has an individual data valid bit for audio and telecom A/D samples. Whenever these bits are set in the data frame returned from the codec to the MCP, the audio and telecom data is taken from the frame and placed in their respective receive FIFO. There are two different modes of operation to control the setting of the audio and telecom data valid bits. The UCB1100 uses both modes. In the first mode, a data valid bit is set any time a frame contains "reliable" data, (i.e., the codec is enabled and at least one A/D sample has been taken). In this mode, once the data valid bit is set, it remains set until the codec A/D input is disabled. In the second mode, the codec only sets the data valid bit corresponding to a new A/D sample. Once, the data is transmitted to the MCP within a receive data frame, the data valid bit is reset to zero for subsequent data frames until a new A/D sample is triggered. 3.8.2.4 MCP FIFO Operation
The MCP contains two 8-word deep, 16-bit audio/telecom transmit FIFOs and two 12-word deep, 16-bit audio/telecom receive FIFOs. As in the previous section, the following description refers to the audio codec for brevity; however, all concepts apply to the telecom portion as well. For each incoming data frame, if the audio data valid bit is set, the 16-bit audio A/D sample is extracted and placed in the audio receive FIFO. Nevertheless, note that the MCP also supports a mode in which the audio data valid bits are ignored, and a number of the incoming frame samples are not stored in the receive FIFOs. For instance, this may happen after the first sample (of an incoming frame sequence) is saved to the FIFO, and the MCP's audio sample rate counter is used to determine when a new A/D sample has been taken and is available within the incoming frame. Audio data is transferred from the incoming data frames to the received FIFO only if the audio enable bit is set within the MCP's status register. A set of input and sample counter value conditions determine whether the audio enable bits are 1 or 0. The MCP's audio sample rate counters are used to trigger when new D/A conversions are to be transmitted to the codec. The user should take care in ensuring sample rate counters in the MCP are synchronized with the respective sample rate counters in the codec, as described previously. When the audio enable status bit transitions from a 0 to a 1 within the MCP status register, the next available entry of data is taken from the audio transmit FIFO and is placed within the correct field in the MCP's serial shifter. This value is then continuously transferred by the MCP in each data frame to the codec. The codec only uses the value when its audio sample rate counter decrements to zero. After the audio D/A conversion is made, both the codec and the MCP's audio sample rate counters reload with their modulus value. This reload triggers the audio transmit FIFO to transfer the next available entry of data to the MCP's serial shifter. Again, this value is continuously transmitted to the codec in each data frame until it is used in the next audio D-to-A conversion. The width of the audio and telecom FIFOs is 16 bits. However, in the UCB1100 the audio codec's sample/conversion data size is 12 bits and the telecom is 14 bits. Samples are left justified within the 16-bit audio and telecom data fields in the MCP frame, as well as within the transmit and receive
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FIFOs. The user must ignore the non-significant bits. Figure 3-6. Format for the Audio and Telecom FIFOs shows the required data alignment in the for the transmit and receive audio and telecom FIFOs.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Audio Data
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Telecom Data
Figure 3-6. Format for the Audio and Telecom FIFOs
3.8.2.5
MCP Codec Control Register Data Transfer
The UCB1100 contains sixteen 16-bit registers used to configure the chip, store touch-screen and ADC samples, as well as digital I/O pin state and edge interrupt status. These registers are read and written via the MCP's serial interface using three fields of the MCP's data frame. Referring to Table 3-3, bits 15:0 contain the codec register value read from or written to the off-chip codec, bits 46:43 contain the register address of the current read or write, and Bit 42 is used by the MCP to indicate a read or write cycle to the codec. These fields are configured by the CPU by writing to MCP Data Register 2 and are then transmitted to the off-chip codec. These fields are also received in every data frame, transmitted to the MCP from the codec, and are placed in MCP Data Register 2 (MCDR2), which in turn can be read by the CPU. Note that the contents of the addressed register, which are sent along with the rest of the frame data to the codec, are returned in the receive data frame regardless of the state of the read/write bit. Thus for write cycles, both a write and a read occurs, and for read cycles, only a read occurs. A codec register write is performed by writing a value to the MCDR2, or Frame Control Data Receive/Transmit Register, which contains the value to store to the codec register, the address of the codec register, and the read/write bit set to one. Once this register is written, its contents are transferred to the correct fields within the serial shifter on the next rising-edge of the SIBSYNC signal. The register information is transmitted to the UCB1100 during subframe 0, and the value is written to the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The control register value and address are also returned to the MCP and stored in MCDR2. Typically, the read/write bit is zero in the return frame. Because the addressed register is updated at the end of subframe 0, the data returned during the frame in which the write occurred represents the previous contents of the register. The updated value is returned during the next data frame. A register read is performed by writing a value to MCDR2 which contains the address of the register and the read/write bit set to a zero. Again, the data is transferred to the serial shifter on the next risingedge of the SIBSYNC signal and is transmitted to the UCB1100 during subframe 0. Because the address and read/write control bit fields occur near the beginning of the serial stream output (or, in other words, towards the end of the subframe -- Bit 63), the codec performs the read immediately 58
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after the read/write bit is received (during the 41st bit of the frame). The value contained within the addressed register is sent back to the MCP in the same data frame. Once the codec control register is written with a value to execute a read or write, the operation is performed every MCP data frame until a new value is written to the register. Thus, continual reads or writes are made to the addressed codec register until a new read or write operation is configured. 3.8.3 * * ADC Interface -- Master Mode Only SSI1 (Synchronous Serial Interface) In the default mode, the device is compatible with the MAXIM MAX148/9 in external clock mode. Similar SPI or Microwire compatible devices can be connected directly to the EP7211. In the extended mode and with negative-edge triggering selected (the ADCCON and ADCCKNSEN bits are set, respectively, in the SYSCON3 register), this device can be interfaced to Analog Devices' AD7811/12 chip using NADCCS as a common RFS/TFS line. Other features of the devices, including power management, can be utilized by software and the use of the GPIO pins.
The first synchronous serial interface allows interfacing to the following peripheral devices:
*
The clock output frequency is programmable and only active during data transmissions to save power. There are four output frequencies selectable, which will be slightly different depending whether the device is operating in a 13 MHz mode or a 18.432 MHz-73.728 MHz mode (see Table 3-14. ADC Interface Operation Frequencies). The required frequency is selected by programming the corresponding bits 16 and 17 in the SYSCON1 register. The sample clock (SMPCLK) always runs at twice the frequency of the shift clock (ADCCLK).
Table 3-14. ADC Interface Operation Frequencies
SYSCON1 Bit 17
0 0 1 1
SYSCON1 Bit 16
0 1 0 1
13.0 MHz Operation ADCCLK Frequency (kHz)
4.2 16.9 67.7 135.4
18.432-73.728 MHz Operation ADCCLK Frequency (kHz)
4 16 64 128
The output channel is fed by an 8-bit shift register when the ADCCON bit of SYSCON3 is clear. When ADCCON is set, up to 16 bits of configuration command can be sent, as specified in the SYNCIO register. The input channel is captured by a 16-bit shift register. The clock and synchronization pulses are activated by a write to the output shift register. During transfers the SSIBUSY (synchronous serial interface busy) bit in the system status flags register is set. When the transfer is complete and valid data is in the 16-bit read shift register, the SSEOTI interrupt is asserted and the SSIBUSY bit is cleared. An additional sample clock (SMPCLK) can be enabled independently and is set at twice the transfer clock frequency.
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This interface has no local buffering capability and is only intended to be used with low bandwidth interfaces, such as for a touch-screen ADC interface. 3.8.4 Master/Slave SSI2 (Synchronous Serial Interface 2)
A second SPI/Microwire interface with full master/slave capability is provided by the EP7211. Data rates in slave mode are theoretically up to 512 kbps, full duplex, although continuous operation at this data rate will give an interrupt rate of 2 kHz, which is too fast for many operating systems. This would require a worst case interrupt response time of less than 0.5 ms and would cause loss of data through TX underruns and RX overruns. The interface is fully capable of being clocked at 512 kHz when in slave mode. However, it is anticipated that external hardware will be used to frame the data into packets. Therefore, although the data would be transmitted at a rate of 512 kbps, the sustained data rate would in fact only be 85.3 kbps (i.e., 1 byte every 750 s). At this data rate, the required interrupt rate will be greater than the 1 ms, which is acceptable. There are separate half-word-wide RX and TX FIFOs (16 half-words each) and corresponding interrupts which are generated when the FIFO's are half-full or half-empty as appropriate. The interrupts are called SS2RX and SS2TX, respectively. Register SS2DR is used to access the FIFOs. There are five pins to support this SSI port: SSIRXDA, SSITXFR, SSICLK, SSITXDA, and SSIRXFR. The SSICLK, SSIRXDA, SSIRXFR, and SSITXFR signals are inputs and the SSITXDA signal is an output in slave mode. In the master mode, SSICLK, SSITXDA, SSITXFR, and SSIRXFR are outputs and SSIRXDA is an input. Master mode is enabled by writing a one to the SS2MAEN bit (SYSCON2[9]). When the master/slave SSI is not required, to save power it can be disabled by writing a zero to the SS2TXEN and the SS2RXEN bits also within the system control register 2 (SYSCON2[4] [7]). When set, these two bits independently enable the transmit and receive sides of the interface. The master/slave SSI is synchronous, full duplex, and capable of supporting serial data transfers between two nodes. Although the interface is byte-oriented, data is loaded in blocks of two bytes at a time. Each data byte to be transferred is marked by a frame sync pulse, lasting one clock period, and located one clock prior to the first bit being transferred. Direction of the SSI2 ports, in slave mode, is shown in Figure 3-7. SSI2 Port Directions in Slave and Master Mode.
Slave 7211 SSIRXFR SSITXFR SSICLK SSIRXDA Master 7211 SSIRXFR SSITXFR SSICLK SSITXDA
SSITXDA
SSIRXDA
Figure 3-7. SSI2 Port Directions in Slave and Master Mode
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Data on the link is sent MSB first and coincides with an appropriate frame sync pulse, of one clock in duration, located one clock prior to the first data bit sent (i.e., MSB). It is not possible to send data LSB first. When operating in master mode, the clock frequency is selected to be the same as the ADC interface's (master mode only SSI1) -- that is, the frequencies are selected by the same bits 16 and 17 of the SYSCON1 register (i.e., the ADCKSEL bits). Thus, the maximum frequency in master mode is 128 kbytes/s. The interface will support continuous transmission at this rate assuming that the OS can respond to the interrupts within 1 ms to prevent over/underruns.
NOTE: To allow synchronization to the incoming slave clock, the interface enable bits will not take effect until one SSICLK cycle after they are written and the value read back from SYSCON2. The enable bits reflect the real status of the enables internally. Hence, there will be a delay before the new value programmed to the enable bits can be read back.
The timing diagram for this interface can be found in the AC Characteristics section of this document. 3.8.4.1 Read Back of Residual Data
All writes to the transmit FIFO must be in half-words (i.e., in units of two bytes at a time). On the receive side, it is possible that an odd number of bytes will be received. Bytes are always loaded into the receive FIFO in pairs, so in the case of a single residual byte remaining at the end of a transmission, it will be necessary for the software to read the byte separately. This is done by reading the status of two bits in the SYSFLG2 register to determine the validity of the residual data. These two bits (RESVAL, RESFRM) are both set high when a residual is valid; RESVAL is cleared on either a new transmission or on reading of the residual bit by software. RESFRM is cleared only on a new transmission. By popping the residual byte into the RX FIFO and then reading the status of these bits it is possible to determine if a residual bit has been correctly read. Figure 3-8. Residual Byte Reading illustrates this procedure. The sequence is as follows: read the RESVAL bit, if this is a 0, no action needs to be taken. If this is a 1, then pop the residual byte into the FIFO by writing to the SS2POP location. Then read back the two status bits RESVAL and RESFRM. If these bits read back 01, then the residual byte popped into the FIFO is valid and can be read back from the SS2DR register. If the bits are not 01, then there has been another transmission received since the residual read procedure has been started. The data item that has been popped to the top of the FIFO will be invalid and should be ignored. In this case, the correct byte will have been stored in the most significant byte of the next half-word to be clocked into the FIFO.
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NOTE: All the writes/reads to the FIFO are done word at a time (data on the lower 16 bits is valid and upper 16 bits are ignored)...
Residual bit valid
00
New RX byte received
11
Pop FIFO New RX byte received
01
Figure 3-8. Residual Byte Reading
Software manually pops the residual byte into the RX FIFO by writing to the SS2POP location (the value written is ignored). This write will strobe the RX FIFO write signal, causing the residual byte to be written into the FIFO. 3.8.4.2 Support for Asymmetric Traffic
The interface supports asymmetric traffic (i.e., unbalanced data flow). This is accomplished through separate transmit and receive frame sync control lines. In operation, the receiving node receives a byte of data on the eight clocks following the assertion of the receive frame sync control line. In a similar fashion, the sending node can transmit a byte of data on the eight clocks following the assertion of the transmit frame sync pulse. There is no correlation in the frequency of assertions of the RX and TX frame sync control lines (SSITXFR and SSIRXFR). Hence, the RX path may bear a greater data throughput than the TX path, or vice versa. Both directions, however, have an absolute maximum data throughput rate determined by the maximum possible clock frequency, assuming that the interrupt response of the target OS is sufficiently quick. 3.8.4.3 Continuous Data Transfer
Data bytes may be sent/received in a contiguous manner without interleaving clocks between bytes. The frame sync control line(s) are eight clocks apart and aligned with the clock representing bit D0 of the preceding byte (i.e., one bit in advance of the MSB). 3.8.4.4 Discontinuous Clock
In order to save power during the idle times, the clock line is put into a static low state. The master is responsible for putting the link into the Idle State. The Idle State will begin one clock, or more, after the last byte transferred and will resume at least one clock prior to the first frame sync assertion. To disable the clock, the TX section is turned off. 62
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In Master mode, the design does not support the discontinuous clock. 3.8.4.5 Error Conditions
RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register. This register should be accessed at periodic intervals by the application software. The status register should be read each time the RX FIFO interrupts are generated. At this time the error condition (i.e., overrun flag) will indicate that an error has occurred but cannot convey which byte contains the error. Writing to the SRXEOF register location clears the overrun flag. TX FIFO underflow condition is detected and conveyed via a bit in the SYSFLG2 register, which is accessed by the application software. A TX underflow error is cleared by writing data to be transmitted to the TX FIFO. 3.8.4.6 Clock Polarity
Clock polarity is fixed. TX data is presented on the bus on the rising edge of the clock. Data is latched into the receiving device on the falling edge of the clock. The TX pin is held in a tristate condition when not transmitting. 3.9 LCD Controller with Support for On-Chip Frame Buffer The LCD controller provides all the necessary control signals to interface directly to a single panel multiplexed LCD. The panel size is programmable and can be any width (line length) from 32 to 1024 pixels in 16 pixel increments. The total video frame buffer size is programmable up to 128 Kbytes. This equates to a theoretical maximum panel size of 1024 x 256 pixels in 4-bits-per-pixel mode. The video frame buffer can be located in any portion of memory controlled by the chip selects, or system DRAM. Its start address will be fixed at address 0x0000000 within each chip select or DRAM bank. The start address of the LCD video frame buffer is defined in the FBADDR register bits [3:0]. These bits become the most significant nibble of the external address bus. The default start address is 0xC000 0000 (FBADDR = 0xC). A system can be built using no DRAM and the on-chip SRAM (OCSR) will then serve as the LCD video frame buffer and miscellaneous data store. The LCD video frame buffer start address should be set to 0x6 in this option. Programming of the register FBADDR is only permitted when the LCD is disabled (this is to avoid possible cycle corruption when changing the register contents while a LCD DMA cycle is in progress). There is no hardware protection to prevent this. It is necessary for the software to disable the LCD controller before reprogramming the FBADDR register. Full address decoding is provided for the OCSR, up to the maximum video frame buffer size programmable into the LCDCON register. Beyond this, the address is wrapped around. The frame buffer start address must not be programmed to 0x4 or 0x5 if either CL-PS6700 interface is in use (PCMEN1 or PCMEN2 bits in the SYSCON2 register are enabled). FBADDR should never be programmed to 0x7 or 0x8, as these are the locations for the onchip Boot ROM and internal registers. The screen is mapped to the video frame buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes or words in the video RAM. The video frame buffer can be accessed word wide as pixel 0 is mapped to the LSB in the buffer such that the pixels are arranged in a Little Endian manner.
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The pixel bit rate, and hence the LCD refresh rate, can be programmed from 18.432 MHz to 576 kHz when operating in 18.432-73.728 MHz mode, or 13 MHz to 203 kHz when operating from a 13 MHz clock. The LCD controller is programmed by writing to the LCD control register (LCDCON). The LCDCON register should not be reprogrammed while the LCD controller is enabled. The LCD controller also contains two 32-bit palette registers, which allow any 4-, 2-, or 1-bit pixel value to be mapped to any of the 16 grey scale values available. The required DMA bandwidth to support a 1/2 VGA panel displaying 4-bits-per-pixel data at an 80 Hz refresh rate is approximately 6.2 Mbytes/sec. Assuming the frame buffer is stored in a 32-bit wide, 50 ns EDO DRAM bank, the maximum theoretical bandwidth available is 86 Mbytes/sec at 36.864 MHz, or 29.7 Mbytes/sec at 13 MHz. If a 16-bit wide, 50 ns EDO DRAM bank is used, this drops to 30 Mbytes/sec at 36.864 MHz; still leaving sufficient bandwidth for other memory activity. The LCD controller uses a nine stage 32-bit wide FIFO to buffer display data. The LCD controller requests new data when there are five words remaining in the FIFO. This means that for a 1/2 VGA display at 4-bits-per-pixel and 80 Hz refresh rate, the maximum allowable DMA latency is approx. 3.2 s (640 x 240 x 4bpp x 80 Hz/8 bits/byte x 5 words (=20 bytes) = 3.2 s). The worst-case latency is the total number of cycles from when the DMA request appears to when the first DMA data word actually becomes available at the FIFO. DMA has the highest priority, so it will always happen next in the system. The worst case latency will occur when the CPU is doing a STM (store multiple) instruction of all 16 registers to DRAM, which it has to complete before the DMA can get access to the bus. The maximum number of cycles required is 36 from the point at which the DMA request occurs to the point at which the STM is complete (see DRAM timing diagrams), then another 6 cycles before the data actually arrives at the FIFO from the first DMA read. This creates a total of 42 cycles. Assuming the frame buffer is located in 32-bit wide, 70 ns FPM or EDO DRAM memory, the worst case latency is almost exactly 3.2 s, with 13 MHz page mode cycles. With each cycle consuming ~77 ns (i.e., 1/13 MHz), the value of 3.2 s comes from 42 cycles x 77 ns/cycle = ~3.23 s. If 16-bit wide, 70ns FPM or EDO DRAM is being used, then the worst case latency will double. In this case, the maximum permissible display size will be halved, to approx. 320 x 240 pixels, assuming the same pixel depth and refresh rate has to be maintained. If the frame buffer is to be stored in static memory, then further calculations must be performed. If 18 MHz mode is selected, and 32-bit wide, 70 ns FPM or EDO DRAM is being used, then the worst case latency will be 2.26 s (i.e., 42 cycles x 54 ns/cycle). If 36 MHz mode is selected, and 32-bit wide, 50 ns EDO DRAM is being used, then the worst case latency drops down to 1.49 s. This calculation is a little more complex for 36 MHz mode of operation. The total number of cycles = (12 x 4) + 7 = 55. Thus, 55 x 27 ns = ~1.49 s.
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Figure 3-9. Video Buffer Mapping shows the organization of the video map for all combinations of bits per pixel.
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Grey scale
Grey scale
Bit 0 Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
4 Bits per pixel
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Grey scale Grey scale
Grey scale
Grey scale
Bit 0
Bit 1 Bit 2 Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
2 Bits per pixel
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Grey scale
Grey scale
Grey scale Grey scale
Bit 0 Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
1 Bit per pixel; in the normal Operating State
Pixel 1 Pixel 2 Pixel 3 Pixel 4
Bit 0 Bit 1 Bit 2
Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
1 Bit per pixel; in the Standby State
Figure 3-9. Video Buffer Mapping
The refresh rate is not affected by the number of bits per pixel; however the LCD controller fetches twice the data per refresh for 4-bits-per-pixel compared to 2-bits-per-pixel. The main reason for reducing the number of bits per pixel is to reduce the power consumption of the memory where the video frame buffer is mapped.
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3.10 Internal UARTs (Two) and SIR Encoder The EP7211 contains two built-in UARTs that offers similar functionality to National Semiconductor's 16C550A device. Both UARTs can support bit rates of up to 115.2 Kbps and include two 16-byte FIFOs: one for receive and one for transmit. One of the UARTs (UART1) supports the three modem control input signals CTS, DSR and DCD. The additional RI input, and RTS and DTR output modem control lines are not explicitly supported but can be implemented using GPIO ports in the EP7211. UART2 has only the RX and TX pins. UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). Three interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can be generated by UART2: RX and TX. The RX interrupt is asserted when the RX FIFO becomes half full or if the FIFO is non-empty for longer than three character length times with no more characters being received. The TX interrupt is asserted if the TX FIFO buffer reaches half empty. The modem status interrupt for UART1 is generated if any of the modem status bits change state. Framing and parity errors are detected as each byte is received and pushed onto the RX FIFO. An overrun error generates an RX interrupt immediately. All error bits can be read from the 11-bit wide data register. The FIFOs can also be programmed to be one byte depth only (i.e., like a conventional 16450 UART with double buffering). The EP7211 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a postprocessing stage on the output of UART1. This encoder can be optionally switched in to the TX and RX signals of UART1, so that these can be used to drive an infrared interface directly. If the SIR protocol encoder is enabled, the UART TXD1 line is held in the passive state and transitions of the RXD1 line will have no effect. The IrDA output pin is LEDDRV, and the input from the photodiode is PHDIN. Modem status lines will cause an interrupt (which can be masked) irrespective of whether the SIR interface is being used. Both the UARTs operate in a similar manner to the industry standard 16C550A. When CTS is deasserted on the UART, the UART does not stop shifting the data. It relies on software to take appropriate action in response to the interrupt generated. Baud rates supported for both the UARTs are dependent on frequency of operation. When operating from the internal PLL, the interface supports various baud rates from 115.2 kbps downwards. The master clock frequency is chosen so that most of the required data rates are obtainable exactly. When operating with a 13.0 MHz external clock source, the baud rates generated will have a slight error, which is less than or equal to 0.75%. The rates obtainable from the 13 MHz clock include 9.6 k, 19.2 k, 38 k, 58 k and 115.2 kbps. See Section 5.9.2 in the register programming section of this spec for full details of the available bit rates in the 13 MHz mode. 3.11 Timer Counters Two identical timer counters are integrated into the EP7211. These are referred to as TC1 and TC2. Each timer counter has an associated 16-bit read/write data register and some control bits in the system control register. Each counter is loaded with the value written to the data register 66
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immediately. This value will then be decremented on the second active clock edge to arrive after the write (i.e., after the first complete period of the clock). When the timer counter under flows (i.e., reaches 0), it will assert its appropriate interrupt. The timer counters can be read at any time. The clock source and mode are selectable by writing to various bits in the system control register. When run from the internal PLL, 512 kHz and 2 kHz rates are provided. When using the 13 MHz external source, the default frequencies will be 541 kHz and 2.115 kHz, respectively. However, only in nonPLL mode, an optional divide by 26 frequency can be generated (thus generating a 500 kHz frequency when using the 13 MHz source). This divider is enabled by setting the OSTB (Operating System Timing Bit) in the SYSCON2 register (Bit 12). When this bit is set high to select the 500 kHz mode, the 500 kHz frequency is routed to the timers instead of the 541 kHz clock. This does not affect the frequencies derived for any of the other internal peripherals.
NOTE: When the EP7211 is in the Standby State, the timer counters are disabled.
The timer counters can operate in two modes: free running or pre-scale. 3.11.1 Free Running Mode In the free running mode, the counter will wrap around to 0xFFFF when it under flows and it will continue to count down. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock. 3.11.2 Prescale Mode In the prescale mode, the value written to TC1 or TC2 is automatically re-loaded when the counter under flows. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock. This mode can be used to produce a programmable frequency to drive the buzzer (i.e., with TC1) or generate a periodic interrupt. 3.12 Realtime Clock The EP7211 contains a 32-bit realtime clock (RTC). This can be written to and read from in the same way as the timer counters but it is 32 bits wide. The RTC is always clocked at 1 Hz, generated from the 32.768 kHz oscillator. It also contains a 32-bit output match register; this can be programmed to generate an interrupt when the time in the RTC matches a specific time written to this register. The RTC can only be reset by an NPOR cold reset. Because the RTC data register is updated from the 1 Hz clock derived from the 32 kHz source, which is asynchronous to the main memory system clock, the data register should always be read twice to ensure a valid and stable reading. This also applies when reading back the RTCDIV field of the SYSCON1 register, which reflects the status of the six LSBs of the RTC counter. 3.13 Dedicated LED Flasher The LED flasher feature enables an external pin (PD[0]/LEDFLSH) to be toggled at a programmable rate and duty ratio -- with the intention that the external pin is connected to an LED. This module is driven from the RTC's 32.768 kHz oscillator and allows it to work in all running modes because no
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CPU intervention is needed once its rate and duty ratio have been configured (via the LEDFLSH register). The LED flash rate period can be programmed for 1, 2, 3, or 4 seconds. The duty ratio can be programmed such that the mark portion can be 1/16, 2/16, 3/16, ..., 16/16 of the full cycle. The external pin can provide up to 4 mA of drive current. 3.14 Two PWM Interfaces Two Pulse Width Modulator (PWM) duty ratio clock outputs are provided by the EP7211. When the device is operating from the internal PLL, this will run at a frequency of 96 kHz. These signals are intended for use as drives for external DC-to-DC converters in the Power Supply Unit (PSU) subsystem. External input pins that would normally be connected to the output from comparators monitoring the external DC-to-DC converter output are also used to enable these clocks. These are the FB[0:1] pins. The duty ratio (and hence PWMs on time) can be programmed from 1 in 16 to 15 in 16. The sense of the PWM drive signal (active high or low) is determined by latching the state of this drive signal during power on reset (i.e., a pull-up on the drive signal will result in a active low drive output, and visa versa). This allows either positive or negative voltages to be generated by the external DC-to-DC converter. PWMs are disabled by writing zeros into the drive ratio fields in the PMPCON Pump Control register.
NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the FB pins. The clocks that source the PWMs are disabled when the drive ratio fields are zeroed.
3.15 State Control The EP7211 supports the following Power Management States: Standby, Idle, and Operating. In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the CLKEN functionality to allow an external oscillator to be disabled in the 13 MHz mode. Either RUN or CLKEN functionality can be selected according to the state of the CLKENSL bit in the SYSCON2 register. The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator is shut down). When the 18.432-73.728 MHz mode is selected, the PLL will be shut down. In the 13 MHz mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be used to disable an external oscillator.
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Table 3-15. Peripheral Status in Different Power Management States
Address (W/B)
DRAM Control UARTs LCD FIFO LCD ADC Interface SSI2 Interface MCP Interface Codec Timers RTC LED Flasher DC-to-DC CPU Interrupt Control PLL/CLKEN Signal
Operating
On On On On On On On On On On On On On On On
Idle
On On On On On On On On On On On On Off On On
Standby
SELFREF Off Reset Off Off Off Off Off Off On On Off Off On Off
NPOR RESET
Off Reset Reset Reset Reset Reset Reset Reset Reset On Reset Reset Reset Reset Off
NRESET RESET
SELFREF Reset Reset Reset Reset Reset Reset Reset Reset On Reset Reset Reset Reset Off
In the Standby State, all the system memory and state is maintained and the system time is kept upto-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the low power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal is driven low when in the Standby State. This signal can be used externally in the system to power down other system modules. Whenever the EP7211 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are powered-down from draining current. Also, the internal peripheral's signals get set to their Reset State. When first powered, or reset by the NPOR (Not Power On Reset) signal, the EP7211 is forced into the Standby State. This is known as a cold reset, and is the only completely asynchronous reset to the EP7211. When leaving the Standby State after a cold reset, external wake up is the only way for waking up the device. When leaving the Standby State after non-cold reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Operating State can be caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when entering the Standby State from the Operating State, the software will leave some interrupt sources enabled. Once the refresh enable register bit is enabled for the DRAMs, any transition to the Standby State will force the DRAMs to the self-refresh state before stopping the PLL or external oscillator.
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NOTE: The CPU cannot be awakened by the TINT, WEINT, and BLINT interrupts when in the Standby State.
Typically, software writes to the Standby internal memory location to cause the transition from the Operating State to the Standby State. Before entering the Standby State, if external I/O devices (such as the CL-PS6700s connected to NCS[4] or NCS[5]) are in use, the software must check to ensure that they are idle before issuing the write to the Standby State location. Before entering the Standby State, the software must properly disable the MCP. Failing to do so will result in higher than expected power consumption in the Standby State, as well as unpredictable operation of the MCP. The MCP can be re-enabled after transitioning back to the Operating State. The system can also be forced into the Standby State by hardware if the NPWRFL or NURESET inputs are forced low. In this case the transition is synchronized with DRAM cycles to avoid any glitches or short cycles. The only exit from the Standby State is to the Operating State. The system will only transition to the Operating State from the Standby State under the following conditions: when the NPWRFL input pin is high and either the NEXTPWR input pin is low or the BATOK input pin is high. This prevents the system from starting when the power supply is inadequate (e.g., the main batteries are low), corresponding to a low level on NPWRFL or BATOK. From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running, the EP7211 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock is applied, there will be a delay of about eight clock cycles before the CPU is first clocked. This is to allow the clock to the CPU to settle. During the Standby State, the UARTs are disabled and cannot detect any activity (e.g., start bit) on the receiver. If this functionality is required then this can be accomplished in software by the following method: 1) Permanently connect the RX pin to one of the active low external interrupt pins. 2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is enabled. 3) Send a preamble that consists of one start bit, 8-bits of zero, and one stop bit. This will cause the EP7211 to wake and execute the enabled interrupt vector. The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the preamble, the timing of the sample point will be off-center during the preamble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured correctly. If in the Operating State, the Idle State can be entered by writing to a special internal memory location in the EP7211. If an interrupt or wakeup event occurs, the EP7211 will return immediately back to the Operating Stateand execute the next instruction.
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In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it waits for an event such as a key press to generate an interrupt, or a rising edge on the external WAKEUP pin. The PLL (in 18.432-73.728 MHz mode) or the external 13 MHz clock source always remains active in the Idle State. Figure 3-10. State Diagram shows a state diagram for the EP7211.
Interrupt or rising wakeup
Standby
Write to standby location, power fail, or user reset Interrupt, rising wakeup
Operating
Write to halt location
Idle
NPOR, power fail, or user reset
Figure 3-10. State Diagram
3.16 Resets There are three asynchronous resets to the EP7211, these are NPOR, NPWRFL and NURESET. If any of these is active, a system reset is generated internally. This will clear all internal registers in the EP7211 to zero (except the DRAM refresh period register (DRFPR), and the RTC data and match registers, which are only cleared by an active NPOR). This ensures that the DRAM contents and system time is preserved through a user reset or power fail condition. Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7211 returns to the Operating State. Internal to the EP7211, three different signals are used to reset storage elements. These are NPOR, NSYSRES and NSTBY. NPOR is an external signal. NSTBY is equivalent to the external RUN signal. NPOR (Not Power On Reset) is the highest priority reset signal. When active (low), it will reset all storage elements in the EP7211. NPOR active forces NSYSRES and NSTBY active. NPOR will only be active after the EP7211 is first powered up and not during any other resets. NPOR active will clear all flags in the status register apart from the cold reset flag (CLDFLG) bit, which is set. NSYSRES (Not System Reset) is generated internally to the EP7211 if NPOR, NPWRFL or NURESET are active. It is the second highest priority reset signal, used to asynchronously reset most internal registers in the EP7211. NSYSRES active forces NSTBY and RUN low. NSYSRES is used to reset the EP7211 and force it into the Standby State with no co-operation from software. The CPU is also reset. The memory controller will place all DRAMs in self refresh mode, thus
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preserving the contents through a system reset. This is the reason the DRAM refresh period register is not cleared by a system reset. The NSTBY and RUN signals are high when the EP7211 is in the Operating or Idle States and low when in the Standby State. The main system clock is valid when NSTBY is high. The NSTBY signal will disable any peripheral block that is clocked from the master clock source (i.e., everything except for the RTC). In general, a system reset will clear all registers and NSTBY will disable all peripherals that require a main clock. The following peripherals are always disabled by a low level on NSTBY: two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI interfaces. In addition, when in the Standby State, the LCD controller and PWM drive are also disabled. When operating from an external 13 MHz oscillator which has become disabled in the Standby State by using the CLKEN signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 s from the rising edge of the CLKEN signal. 3.17 Clocks There are two clocking modes for the EP7211. Either an external clock input can be used or the onchip PLL. The clock source is selected by a strapping option on Port E, Pin 2 (PE[2]). If PE[2] is high at the rising edge of NPOR (i.e., upon power-up), the external clock mode is selected. If PE[2] is low, then the on-chip PLL mode is selected. The architecture for the EP7211 device contains several separate sections of logic. Some of them are the ARM720T processor, the peripherals, and the address/data bus sections. The peripherals section has its own dedicated bus structure called the Embedded Peripheral Bus (EPB). From the ARM720T's point of view, the peripherals are strobed devices. Each unique peripheral device does have its own dedicated clock source supplied to it according to its clock frequency requirements. However, when the EP7211 is in the PLL mode, the actual frequencies will be different than when in the external clock mode. See each peripheral device section for more details. The section below describes the clocking for both the ARM720T and address/data bus sections. 3.17.1 On-Chip PLL The ARM720T clock can be programmed to run at 18.432 MHz, 36.864 MHz, 49.152 MHz or 73.728 MHz. The PLL frequency is fixed at twice the highest possible CPU clock frequency (147.456 MHz). The PLL uses an external 3.6864 MHz crystal. On power-up, if the device has been strapped to use the on-chip PLL, then the device will start up with both the ARM720T and address/data buses configured to run at 18.432 MHz by default. After power-up, the clock frequency can be changed by software. If the clock frequency is changed to be 36 MHz, both the ARM720T and the address/data buses will be clocked at 36 MHz as well. When the clock frequency is selected higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does not effect the individual dedicated peripheral clock sources. In other words, all the peripheral clocks are fixed, regardless of the PLL mode clock speed selected for the ARM720T. 72
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When the PLL mode is selected, the EXPCLK pin becomes an output. This output signal can then be used to supply a synchronized clock source to external devices (e.g., a CL-PS6700 PC Card controller device). When in the PLL mode, PE[2] can be used as a GPIO after power-up.
NOTE: After modifying the CLKCTL[1:0] bits, the next instruction should always be a NOP.
3.17.2 External Clock Input (13 MHz) An external 13 MHz crystal oscillator can be used to drive all of the EP7211. On power-up, if the device has been strapped to use the external clock, the ARM720T and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode. In this configuration, the PLL will not be used at all. The clock signal should be connected to the EXPCLK pin of the EP7211. In this mode, EXPCLK becomes an input. If the CLKENSL bit is set low, then pin CLKEN/RUN (an output pin) provides the CLKEN signal that can be used to start and stop the external 13 MHz clock source (i.e., the oscillator) used to supply the clock for the EP7211 and the PWM. In this case, when CLKEN is active (high), it can be used to enable the external 13 MHz clock source, and when low, it can be used to disable it. When the Standby State is entered in 13 MHz mode, the 13 MHz source is disabled at the EXPCLK input pin pad until the Standby State is exited. Therefore, the external clock source does not have to be disabled to be able to disable the clocks internally. When in the 13 MHz mode, if the CLKENSL bit is set high, then the Standby State is exited immediately on a wakeup event or an enabled interrupt occurring. If CLKENSL is set low, then the EP7211 will set CLKEN high after an interrupt or wakeup event occurs, then wait for between 0.125 s and 0.25 s to allow an external oscillator time to stabilize before the clock is enabled through to the CPU. Only a non-masked interrupt (e.g., realtime clock match), Port A event (corresponding to a keypress), or WAKEUP signal asserted will wakeup the EP7211 out of the Standby State. The timing is shown below for the case where CLKENSL is low:
NOTE: When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from their default value of `00'.
CLKEN timing while entering STDBY mode
13 MHz
CLKEN
Figure 3-11. CLKEN Timing Entering the Standby State
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CLKEN timing -- coming out of STDBY
EXPCLK
(int) RUN
T42
CLKEN Intr./ WAKEUP
NOTE: T42 = 0.125 s to 0.25 s
Figure 3-12. CLKEN Timing Leaving the Standby State
3.18 Dynamic Clock Switching When in the PLL Clocking Mode The clock frequency used for the CPU and the buses is controlled by programming the CLKCTL[1:0] bits in the SYSCON3 register. When this occurs, the state controller switches from the current to the new clock frequency as soon as possible without causing a glitch on the clock signals. The glitch-free clock switching logic waits until the clock that is currently in use and the newly programmed clock source are both low, and then switches from the previous clock to the new clock without a glitch on the clocks. 3.19 Endianness The EP7211 uses a Little Endian configuration for internal registers. However, it is possible to connect the device to a Big Endian external memory system. The bigend bit in the ARM720T control register sets whether the EP7211 treats words in memory as being stored in Big Endian or Little Endian format. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In the Little Endian scheme, the lowest numbered byte in a word is considered to be the least significant byte of the word and the highest numbered byte is the most significant. Byte 0 of the memory system should be connected to data lines 7 through 0 (D[7:0]) in this scheme. In the Big Endian scheme the most significant byte of a word is stored at the lowest numbered byte, and the least significant byte is stored at the highest numbered byte. Therefore, Byte 0 of the memory system should be connected to data lines 31 through 24 (D[31:24]). Load and store are the only instructions affected by the Endianness. The following tables demonstrate the behavior of the EP7211 in Big and Little Endian mode, including the effect of performing non-aligned word accesses. The register definition section of this
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
specification defines the behavior of the internal EP7211 registers in the Big Endian mode in more detail. The NCAS[3:0] lines for DRAM should always be connected with the same byte lane irrespective of the Endianness, such that NCAS[0] will be connected with D[7:0], and NCAS[3] with D[31:24]. Thus, in a Little Endian system, NCAS[0] will be asserted for a read/write to byte 0 of DRAM and in a big Endian system NCAS[3] will be asserted to access byte 0 of DRAM.
Table 3-16. Effect of Endianness on Read Operations
Byte Lanes to Memory/Ports/Registers R0 Contents Address (W/B) Data in Memory Big Endian Memory 7:0
Word + 0 (W) Word + 1 (W) Word + 2 (W) Word + 3 (W) Word + 0 (B) Word + 1 (B) Word + 2 (B) Word + 3 (B) 11223344 11223344 11223344 11223344 11223344 11223344 11223344 11223344 44 44 44 44 dc dc dc 44
Little Endian Memory 7:0
44 44 44 44 44 dc dc dc
15:8
33 33 33 33 dc dc 33 dc
23:1 6
22 22 22 22 dc 22 dc dc
31:2 4
11 11 11 11 11 dc dc dc
15:8
33 33 33 33 dc 33 dc dc
23:1 6
22 22 22 22 dc dc 22 dc
31:2 4
11 11 11 11 dc dc dc 11
Big Endian
11223344 44112233 33441122 22334411 00000011 00000022 00000033 00000044
Little Endian
11223344 44112233 33441122 22334411 00000044 00000033 00000022 00000011
NOTE: dc = don't care
Table 3-17. Effect of Endianness on Write Operations
Byte Lanes to Memory/Ports/Registers Address (W/B) Register Contents 7:0
Word + 0 (W) Word + 1 (W) Word + 2 (W) Word + 3 (W) Word + 0 (B) Word + 1 (B) Word + 2 (B) Word + 3 (B) 11223344 11223344 11223344 11223344 11223344 11223344 11223344 11223344 44 44 44 44 44 44 44 44
Big Endian Memory 15:8
33 33 33 33 44 44 44 44
Little Endian Memory 31:24
11 11 11 11 44 44 44 44
23:16
22 22 22 22 44 44 44 44
7:0
44 44 44 44 44 44 44 44
15:8
33 33 33 33 44 44 44 44
23:16
22 22 22 22 44 44 44 44
31:24
11 11 11 11 44 44 44 44
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Functional Description
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
NOTE: Bold indicates active byte lane.
3.20 Maximum EP7211-Based System A maximum configured system using the EP7211 is shown in Figure 3-13. A Maximum EP7211 Based System. This system assumes all the DRAMs and ROMs are 16-bit wide devices. The keyboard may be connected to more GPIO bits than shown to allow greater than 64 keys, however these extra pins will not be wired into the WAKEUP pin functionality.
DD[3:0]
CRYSTAL
MOSCIN NCS[4] PB0 EXPCLK
CL1 CL2 FM M COL[7:0]
LCD MODULE
D[31:0]
KEYBOARD
PA[7:0] PB[7:0] PD[7:0] PE[2:0] NPOR NPWRFL BATOK NEXTPWR NBATCHG RUN WAKEUP DRIVE[1:0] FB[1:0]
PC CARD SOCKET
CL-PS6700 PC CARD CONTROLLER
A[27:0] NMOE WRITE
NRAS[1] NRAS[0]
EP7211
POWER SUPPLY UNIT AND COMPARATORS
DC INPUT
x16 DRAM x16 DRAM
x16 DRAM x16 DRAM
NCAS[0] NCAS[1] NCAS[2] NCAS[3] NCS[0] NCS[1]
BATTERY
DC-TO-DC CONVERTERS
x16 FLASH x16 FLASH
x16 ROM x6 ROM
CS[n] WORD
SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR LEDDRV PHDIN RXD1/2 TXD1/2 DSR CTS DCD ADCCLK NADCCS ADCOUT ADCIN SMPCLK
CODEC/SSI2/ MCP
IR LED AND PHOTODIODE
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
2x RS-232 TRANSCEIVERS
NCS[2] NCS[3]
ADDITIONAL I/O
BUFFERS AND LATCHES
ADC
DIGITIZER
LEDFLSH
Figure 3-13. A Maximum EP7211 Based System
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
NOTE: A system can only use one of the following peripheral interfaces at any given time: SSI2, codec, or MCP.
3.21 Boundary Scan IEEE 1149.1 compliant JTAG is provided with the EP7211. (It should be noted that a full system reset, BNRES[0] = '0', must be applied to the device initially.)
Table 3-18. Instructions Supported in JTAG Mode
Instruction
BYPASS IDCODE SAMPLE/PRELOAD EXTEST SCAN_N
Code
1111 1110 0011 0000 0010
The INTEST function will not be supported for the EP7211. Additional user-defined instructions exist, but these are not relevant to board-level testing. For further information please refer to the ARM DDI 0087E ARM720T Datasheet Section 8. As there are additional scan-chains within the ARM720T processor, it is necessary to include a scanchain select function -- shown as SCAN_N in Table 3-18. Instructions Supported in JTAG Mode. To select a particular scan chain, this function must be input to the TAP controller, followed by the 4-bit scan-chain identification code. The identification code for the boundary scan chain is 0011. Note that it is only necessary to issue the SCAN_N instruction if the device is already in the JTAG mode. The boundary scan chain is selected as the default on test-logic reset and any of the system resets. The contents of the device ID-register for the EP7211 are shown below:
Version
Part number
Manufacturer ID
00001111000011110000111100001111
This is equivalent to 0F0F0F0F Hex. Note this is the ID-code for the ARM720T processor.
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Functional Description
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
3.22 In-Circuit Emulation 3.22.1 Introduction EmbeddedICE is an extension to the architecture of the ARM family of processors, and provides the ability to debug cores that are deeply embedded into systems. It consists of three parts: 1) A set of extensions to the ARM core 2) The EmbeddedICE macrocell, to provide access the extensions from the outside world 3) The EmbeddedICE interface to provide communication from the EmbeddedICE macrocell and the host computer The EmbeddedICE macrocell is programmed, in a serial fashion, through the TAP controller on the ARM via the JTAG interface. The EmbeddedICE macrocell is by default disabled to minimize power usage, and must be enabled at boot-up to support this functionality. 3.22.2 Functionality The ICEBreaker module consists of two real-time watchpoint units together with a control and status register. One or both of the units can be programmed to halt the execution of the instructions by the ARM processor. Execution is halted when either a match occurs between the values programmed into the ICEBreaker and the values currently appearing on the address bus, data bus, and the various control signals. Any bit can be masked to remove it from the comparison. Either unit can be programmed as a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Using one of these watchpoint units, an unlimited number of software breakpoints (in RAM) can be supported by substitution of the actual code.
NOTE: The EXTERN[1:0] signals from the ICEBreaker module are not wired out in this device. This mechanism is used to allow watchpoints to be dependent on an external event. This behavior can be emulated in software via the ICEBreaker control registers.
A more detailed description is available in the ARM Software Development Toolkit User Guide and Reference Manual. The ICEBreaker module and its registers are fully described in the ARM7TDMI Datasheet, Chapters 8 and 9.
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
4. MEMORY MAP
The lower 2 GByte of the address space is allocated to ROM/SRAM/Flash and expansion space. The 0.5 Gbyte of address space from 0xC0000000 to 0xDFFFFFFF is allocated to DRAM. The remaining 1.5 Gbyte, less 8K for internal registers, is not accessible in the EP7211. The MMU in the EP7211 should be programmed to generate an abort exception for access to this area. Internal peripherals are addressed through a set of internal memory locations from hex address 8000.0000 to 8000.3FFF. These are known as the internal registers in the EP7211. Figure 4-1 shows how the 4-Gbyte address range of the ARM720T processor (as configured within this chip) is mapped in the EP7211. The memory map shown assumes that two CL-PS6700 PC Card controllers are connected. If this functionality is not required, then the NCS4 and NCS5 memory is available as general ROM/SRAM/Flash/Expansion space. The Boot ROM is not fully decoded (i.e., the Boot code will repeat within the 256-Mbyte space from 0x70000000 to 0x80000000). The SRAM is fully decoded up to a maximum size of 128 kbytes. Access to any location above this range will be wrapped to within the range.
Table 4-1. EP7211 Memory Map
Address
0xF000.0000 0xE000.0000 0xD000.0000 0xC000.0000 0x8000.4000 0x8000.2000 0x8000.0000 0x7000.0000 0x6000.0000 0x5000.0000 0x4000.0000 0x3000.0000 0x2000.0000 0x1000.0000 0x0000.0000 Boot ROM (NCS7) SRAM (NCS6) PCMCIA-1 (NCS5) PCMCIA-0 (NCS4) Expansion (CS3) Expansion (CS2) ROM Bank 1 (CS1) ROM Bank 0 (CS0)
Contents
Reserved Reserved DRAM Bank 1 DRAM Bank 0 Unused Internal registers (new) Internal registers (old)
Size
256 Mbytes 256 Mbytes 256 Mbytes 256 Mbytes ~1 Gbyte 8 kbytes 8 kbytes 128 bytes 37.5 kbytes 4 x 64 Mbytes 4 x 64 Mbytes 256 Mbytes 256 Mbytes 256 Mbytes 256 Mbytes
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Memory Map
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5. REGISTER DESCRIPTIONS
5.1 Internal Registers Table 5-1. Internal I/O Memory Locations shows all internal registers in the EP7211, assuming the CPU is configured for operation with a Little Endian memory system. Table 5-2.Port Byte Addresses in Big Endian Mode shows the differences that occur for byte-wide access to Ports A, B, and D with the CPU configured to operate in the Big Endian mode. All the internal registers are inherently Little Endian (i.e., the least significant byte is attached to bits 7 to 0 of the data bus). Hence, the system Endianness affects the addresses required for byte accesses to the internal registers, resulting in a reversal of the byte address required to read/write a particular byte within a register. Note that the internal registers have been split into two groups - the "old" and the "new". The old ones are the same as that used in CL-PS7111 and are there for compatibility. The new registers are for accessing the additional functionality of the MCP interface and the LED flasher. There is no effect on the register addresses for word accesses. Bits A0 and A1 of the internal address bus are only decoded for Ports A, B, and D (to allow read/write to individual ports). For all other registers, bits A0 and A1 are not decoded, so that byte reads will return the whole register contents onto the EP7211's internal bus, from where the appropriate byte (according to the Endianness) will be read by the CPU. For example, to read data back from the DRAM refresh period register (which is only 8 bits wide) requires address 0x80000200 if read as a word (irrespective of Endianness), or as a byte in the Little Endian mode, but a byte read to obtain the register contents in Big Endian mode must output address 0x80000203. To avoid the additional complexity, it is preferable to perform all internal register accesses as word operations, except for ports A to D which are explicitly designed to operate with byte accesses, as well as word accesses. An 8K segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved for internal use in the EP7211. Accesses in this range will not cause any external bus activity unless debug mode is enabled. Writes to bits that are not explicitly defined in the internal area are legal and will have no effect. Reads from bits not explicitly defined in the internal area are legal but will read undefined values. All the internal addresses should only be accessed as 32-bit words and are always on a word boundary, except for the PIO port registers, which can be accessed as bytes. Address bits in the range A0 -A5 are not decoded (except for Ports A-D), this means each internal register is valid for 64 bytes (i.e., the SYSFLG1 register appears at locations 0x8000.0140 to 0x8000.017C). There are some gaps in the register map for backward compatibility reasons, but registers located next to a gap are still only decoded for 64 bytes. The GPIO port registers are byte-wide and can be accessed as a word but not as a half-word. These registers additionally decode A0 and A1. All addresses are in hexadecimal notation.
NOTE: All byte-wide registers should be accessed as words (except Port A to Port D registers, which are designed to work in both word and byte modes). All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified). The registers which interact with the 32 kHz clock or which could change during readback (e.g., RTC data registers, SYSFLG register (lower 6-bits only), the TC1 and 2 data registers, port registers, inter-
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
rupt status registers) should be read twice and compared to ensure that a stable value has been read back.
Table 5-1. CL-PS7111-Compatible
Address
0x8000.0000 0x8000.0001 0x8000.0002 0x8000.0003 0x8000.0040 0x8000.0041 0x8000.0042 0x8000.0043 0x8000.0080 0x8000.00C0 0x8000.0100 0x8000.0140 0x8000.0180 0x8000.01C0 0x8000.0200 0x8000.0240 0x8000.0280 0x8000.02C0 0x8000.0300 0x8000.0340 0x8000.0380 0x8000.03C0 0x8000.0400 0x8000.0440 0x8000.0480 0x8000.04C0 0x8000.0500 0x8000.0540
Name
PADR PBDR -- PDDR PADDR PBDDR -- PDDDR PEDR PEDDR SYSCON1 SYSFLG MEMCFG1 MEMCFG2 DRFPR INTSR1 INTMR1 LCDCON TC1D TC2D RTCDR RTCMR PMPCON CODR UARTDR1 UBLCR1 SYNCIO PALMSW
Default
0 0
RD/WR
RW RW --
Size
8 8 8 8 8 8 8 8 3 3 32 32 32 32 8 32 32 32 16 16 32 32 12 8 8W/11R 32 32 32
Comments
Port A data register Port B data register Reserved Port D data register Port A data direction register Port B data direction register Reserved Port D data direction register Port E data register Port E data direction register System control register 1 System status flags register 1 Expansion and ROM memory configuration register 1 Expansion and ROM memory configuration register 2 DRAM refresh period register Interrupt status register 1 Interrupt mask register 1 LCD control register Read/Write data to TC1 Read/Write data to TC2 Realtime clock data register Realtime clock match register PWM pump control register CODEC data I/O register UART1 FIFO data register UART1 bit rate and line control register Synchronous serial I/O data register for master only SSI Least significant 32-bit word of LCD palette register
0 0 0
RW RW RW --
0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- 0 0 0 0 0 0
RW RW RW RW RD RW RW RW RD RW RW RW RW RW RW RW RW RW RW RW RW
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-1. CL-PS7111-Compatible (cont.)
Address
0x8000.0580 0x8000.05C0 0x8000.0600 0x8000.0640 0x8000.0680 0x8000.06C0 0x8000.0700 0x8000.0740 0x8000.0780 0x8000.07C0 0x8000.0800 0x8000.0840 0x8000.0880- 0x8000.0FFF 0x8000.1000 0x8000.1100 0x8000.1140 0x8000.1240 0x8000.1280 0x8000.12C0- 0x8000.147F 0x8000.1480 0x8000.14C0 0x8000.1500 0x8000.1600 0x8000.16C0 0x8000.1700 0x8000.1800
Name
PALMSW STFCLR BLEOI MCEOI TEOI TC1EOI TC2EOI RTCEOI UMSEOI COEOI HALT STDBY Reserved FBADDR SYSCON2 SYSFLG2 INTSR2 INTMR2 Reserved UARTDR2 UBLCR2 SS2DR SRXEOF SS2POP KBDEOI Reserved
Default
0 -- -- -- -- -- -- -- -- -- -- --
RD/WR
RW WR WR WR WR WR WR WR WR WR WR WR
Size
32 -- -- -- -- -- -- -- -- -- -- --
Comments
Most significant 32-bit word of LCD palette register Write to clear all start up reason flags Write to clear battery low interrupt Write to clear media changed interrupt Write to clear tick and watchdog interrupt Write to clear TC1 interrupt Write to clear TC2 interrupt Write to clear RTC match interrupt Write to clear UART modem status changed interrupt Write to clear CODEC sound interrupt Write to enter the Idle State Write to enter the Standby State Write will have no effect, read is undefined
C 0 0 0 0
RW RW RD RD RW
4 16 16 24 16
LCD frame buffer start address System control register 2 System status register 2 Interrupt status register 2 Interrupt mask register 2 Write will have no effect, read is undefined
0 0 0 -- -- -- --
RW RW RW WR WR WR WR
8W/11R 32 16 -- -- -- --
UART2 Data Register UART2 bit rate and line control register Master/slave SSI2 data Register Write to clear RX FIFO overflow flag Write to pop SSI2 residual byte into RX FIFO Write to clear keyboard interrupt Do not write to this location. A write will cause the processor to go into an unsupported power savings state. Write will have no effect, read is undefined
0x8000.1840- 0x8000.1FFF
Reserved
--
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-2. Internal I/O Memory Locations (EP7211 Only)
Address
0x8000.2000 0x8000.2040 0x8000.2080 0x8000.20C0 0x8000.2100 0x8000.2200 0x8000.2240 0x8000.2280 0x8000.22C0 0x8000.2300- 0xBFFF.FFFF
Name
MCCR MCDR0 MCDR1 MCDR2 MCSR SYSCON3 INTSR3 INTMR3 Ledflsh Reserved
Default
-- 0 0 0 -- 0 0 0 0
RD/WR
RW RW RW RW RD RW RD RW RW
Size
32 32 32 32 32 8 8 8 7
Comments
MCP Control Register MCP Data Register0 MCP Data Register1 MCP Data Register2 MCP Status Register System control register 3 Interrupt status register 3 Interrupt mask register 3 LED Flash control Register This area contains test registers used during manufacturing test. Writes to this area should never be attempted during normal operation as this may cause unexpected behavior. Reads will be undefined.
Table 5-3. Port Byte Addresses in Big Endian Mode
Address
0x8000.0003 0x8000.0002 0x8000.0001 0x8000.0000 0x8000.0043 0x8000.0042 0x8000.0041 0x8000.0040
Name
PADR PBDR -- PDDR PADDR PBDDR -- PDDDR
Default
0 0
RD/WR
RW RW --
Size
8 8 8 8 8 8 8 8
Comments
Port A data register Port B data register Reserved Port D data register Port A data direction register Port B data direction register Reserved Port D data direction register
0 0 0
RW RW RW --
0
RW
All internal registers in the EP7211 are reset (cleared to zero) by a system reset (i.e., NPOR, NRESET, or NPWRFL signals becoming active), except for the DRAM refresh period register (DRFPR), and the realtime clock data register (RTCDR) and match register (RTCMR), which are only reset by NPOR becoming active. This ensures that the DRAM contents and system time preserved through a user reset or power fail condition.
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.1.1
PADR Port A Data Register
ADDRESS: 0x8000.0000 Values written to this 8-bit read/write register will be output on Port A pins if the corresponding data direction bits are set high (port output). Values read from this register reflect the external state of Port A, not necessarily the value written to it. All bits are cleared by a system reset. 5.1.2 PBDR Port B Data Register
ADDRESS: 0x8000.0001 Values written to this 8-bit read/write register will be output on Port B pins if the corresponding data direction bits are set high (port output). Values read from this register reflect the external state of Port B, not necessarily the value written to it. All bits are cleared by a system reset. 5.1.3 PDDR Port D Data Register
ADDRESS: 0x8000.0003 Values written to this 8-bit read/write register will be output on Port D pins if the corresponding data direction bits are set low (port output). Values read from this register reflect the external state of Port D, not necessarily the value written to it. All bits are cleared by a system reset. 5.1.4 PADDR Port A Data Direction Register
ADDRESS: 0x8000.0040 Bits set in this 8-bit read/write register will select the corresponding pin in Port A to become an output, clearing a bit sets the pin to input. All bits are cleared by a system reset. 5.1.5 PBDDR Port B Data Direction Register
ADDRESS: 0x8000.0041 Bits set in this 8-bit read/write register will select the corresponding pin in Port B to become an output, clearing a bit sets the pin to input. All bits are cleared by a system reset. 5.1.6 PDDDR Port D Data Direction Register
ADDRESS: 0x8000.0043 Bits cleared in this 8-bit read/write register will select the corresponding pin in Port D to become an output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.1.7
PEDR Port E Data Register
ADDRESS: 0x8000.0080 Values written to this 3-bit read/write register will be output on Port E pins if the corresponding data direction bits are set high (port output). Values read from this register reflect the external state of Port E, not necessarily the value written to it. All bits are cleared by a system reset. 5.1.8 PEDDR Port E Data Direction Register
ADDRESS: 0x8000.00C0 Bits set in this 3-bit read/write register will select the corresponding pin in Port E to become an output, clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default. 5.2 5.2.1 SYSTEM Control Registers SYSCON1 The System Control Register 1
ADDRESS: 0x8000.0100
7 TC2S 6 TC2M 5 TC1S 4 TC1M 3:0 Keyboard scan
15 SIREN
14 CDENRX
13 CDENTX
12 LCDEN
11 DBGEN
10 BZMOD
9 BZTOG
8 UART1EN
23
22
21
20 IRTXM
19 WAKEDIS
18 EXCKEN
17:16 ADCKSEL
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The system control register is a 21-bit read/write register which controls all the general configuration of the EP7211, as well as modes etc. for peripheral devices. All bits in this register are cleared by a system reset. The bits in the system control register SYSCON1 are defined below.
Bit
0:3
Description
Keyboard scan: This 4-bit field defines the state of the keyboard column drives. The following table defines these states.
Keyboard Scan
0 1 2-7 8 9 10 11 12 13 14 15 4 All driven high All driven low
Column
All high impedance (tristate) Column 0 only driven high all others high impedance Column 1 only driven high all others high impedance Column 2 only driven high all others high impedance Column 3 only driven high all others high impedance Column 4 only driven high all others high impedance Column 5 only driven high all others high impedance Column 6 only driven high all others high impedance Column 7 only driven high all others high impedance
TC1M: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free running mode. TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clearing it sets the clock source to 2 kHz. TC2M: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free running mode. TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clearing it sets the clock source to 2 kHz. UART1EN: Internal UART enable bit. Setting this bit enables the internal UART. BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is selected (i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ bits for more details. BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin is connected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer drive is in the hardware mode. Two hardware sources are available to drive the pin. They are the TC1 or a fixed internally generated clock source. The selection of which source is used to drive the pin is determined by the state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is selected, then the buzzer output pin is connected to the TC1 under flow bit. The buzzer output pin changes every time the timer wraps around. The frequency depends on what was programmed into the timer. See the description of the BUZFREQ and BZTOG bits for more details.
5
6
7
8 9
10
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
16:17
Description
ADCKSEL: Microwire / SPI peripheral clock speed select. This two bit field selects the frequency of the ADC sample clock; this is twice the frequency of the synchronous serial ADC interface clock. The table below shows the available frequencies for operation when in PLL mode. These bits are also used to select the shift clock frequency for the SSI2 interface when set into master mode. The frequencies obtained in 13.0 MHz mode can be found in Table 3-15. ADC Interface Operation Frequencies.
ADCKSEL
00 01 10 11
ADC Sample Frequency (kHz) -- SMPCLK
8 32 128 256
ADC Clock Frequency (kHz) -- ADCCLK
4 16 64 128
11
DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are output as if they were reads or writes to expansion memory addressed by NCS5. NCS5 will still be active in its standard address range. In addition the internal interrupt request and fast interrupt request signals to the ARM720T processor are output on Port E, bits 1 and 2. Note that these bits must be programmed to be outputs before this functionality can be observed. The clock to the CPU is output on Port E, Bit 0 to enable individual accesses to be distinguished. For example, in debug mode: NCS5 = NCS5 or internal I/O strobe PE0 = CLK PE1 = NIRQ PE2 = NFIQ LCDEN: LCD enable bit. Setting this bit enables the LCD controller. CDENTX: Codec interface enable TX bit. Setting this bit enables the codec interface for data transmission to an external codec device. CDENRX: Codec interface enable RX bit. Setting this bit enables the codec interface for data reception from an external codec device. NOTE: Both CDENRX and CDENTX need to be enabled/disabled in TANDEM. SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not enabled. EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously; it is the same speed and phase as the CPU clock and will free run all the time the main oscillator is running if this bit is set. This bit should not be left set all the time for power consumption reasons. If the system enters the Standby State, the EXPCLK will become undefined. If this bit is clear, EXPCLK will be active during memory cycles to expansion slots that have external wait state generation enabled only. WAKEDIS: Setting this bit disables waking up from the Standby State, via the wakeup input. IRTXM: IrDA TX mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means each zero bit transmitted is represented as a pulse of width 3/16th of the bit rate period. Setting this bit means each zero bit is represented as a pulse of width 3/16th of the period of 115,200-bit rate clock (i.e., 1.6 sw regardless of the selected bit rate). Setting this bit will use less power, but will probably reduce transmission distances.
12 13
14
15 18
19 20
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Register Descriptions
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.2
SYSCON2 System Control Register 2
ADDRESS: 0x8000.1100
7 SS2RXEN 6 PC CARD2 5 PC CARD1 4 SS2TXEN 3 KBWEN 2 DRAMSZ 1 KBD6 0 SERSEL
15 Reserved
14 BUZFREQ
13 CLKENSL
12 OSTB
11 Reserved
10 Reserved
9 SS2MAEN
8 UART2EN
This register is an extension of SYSCON1, containing additional control for the EP7211, for compatibility with CL-PS7111. The bits of this second system control register are defined below. The SYSCON2 register is reset to all 0s on power up.
Bit
0
Description
SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external pins. See the table below for the selection options. NOTE: If the MCPSEL bit of SYSCON3 is set, then it overrides the state of the SERSEL bit, and thus the external pins are connected to the MCP interface.
SERSEL Value
0 1
Selected Serial Device to External Pins
Master/slave SSI2 Codec
1
KBD6: The state of this bit determines how many of the Port A inputs are OR'ed together to create the keyboard interrupt. When zero (the reset state), all eight of the Port A inputs will generate a keyboard interrupt. When set high, only Port A bits 0 to 5 will generate an interrupt from the keyboard. It is assumed that the keyboard row lines are connected into Port A. DRAMSZ: Determines width of DRAM memory interface, where:0 = 32-bit DRAM and 1 = 16-bit DRAM. KBWEN: When the KBWEN bit is high, the EP7211 will get woken from a power saving state into the Operating State when a high signal is on one of Port A's inputs (irrespective of the state of the interrupt mask register). This is called the Keyboard Direct Wakeup mode. In this mode, the interrupt request does not have to get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2) Bit 0 is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt. SS2TXEN: Transmit enable for the synchronous serial interface 2. The transmit side of SSI2 will be disabled until this bit is set. When set low, this bit also disables the SSICLK pin (to save power) in master mode, if receive side is low. SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will be disabled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2 interface will be in a power saving state.
2 3
4
7
88
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
5
Description
PC CARD1: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect of this bit is to reassign the functionality of Port B, Bit 0 to the PRDY input from the CL-PS6700 devices, and to ensure that any access to the NCS4 address space will be according to the CL-PS6700 interface protocol. PC CARD2: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect of this bit is to reassign the functionality of Port B, Bit 1 to the PRDY input from the CL-PS6700 devices, and to ensure that any access to the NCS5 address space will be according to the CL-PS6700 interface protocol. UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2. SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be configured for slave mode operation. When high, SSI2 will be configured for master mode operation. This bit also controls the directionality of the interface pins. OSTB: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode. Normally it will be set low, however when set high it will cause a 500 kHz clock to be generated for the timers instead of the 541 kHz which would normally be available. The divider to generate this frequency is not clocked when this bit is set low. CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin. When high, the RUN signal will be output on RUN/CLKEN. BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the source to drive the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the on-chip timer (TC1) is output. When BUZFREQ = 1, a fixed frequency clock is output (500 Hz when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and the BZTOG bits for more details.
6
8 9
12
13
14
DS352PP3 JUL 2001
Register Descriptions
89
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.3
SYSCON3 System Control Register 3
ADDRESS: 0x8000.2200
15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 FASTWAKE
7 VERSN[2]R eserved
6 VERSN[1] Reserved
5 VERSN[0] Reserved
4 ADCCKNSEN
3 MCPSEL
2 CLKCTL1
1 CLKCTL0
0 ADCCON
This register is an extension of SYSCON1 and SYSCON2, containing additional control for the EP7211. The bits of this third system control register are defined below.
Bit
8
Description
FASTWAKE: When set, the device will wake from the Standby State within one to two cycles of a 4 kHz clock. This bit is cleared at power up, and thus the device first starts using the default one to two cycles of the 8 Hz clock. VERSN[2:0]: Additional read-only version bits -- will read `000'. ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the opposite edges are used. MCPSEL: When set selects the MCP. This defaults to either the SSI or codec (i.e., MCPSEL bit is low). ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Configuration Extension field in the SYNCIO register is used for ADC Configuration data and the value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit). CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling. The table below lists the available options.
5:7 4
3 0
1:2
CLKCTL(1:0) Value
00 01 10 11
Processor Frequency
18.432 MHz 36.864 MHz 49.152 MHz 73.728 MHz
ASB and APB Frequency
18.432 MHz 36.864 MHz 36.864 MHz 36.864 MHz
Wait State Scaling
1 2 2 2
NOTE: To determine the number of wait states programmed refer to Table 5-4. Values of the Wait State Field at 13 and 18MHz and Table 5-5. Values of the Wait State Field at 36 MHz. When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from the default value of `00'. Under no circumstances should the CLKCTL bits be changed using a buffered write.
90
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.4
SYSFLG -- The System Status Flags Register
ADDRESS: 0x8000.0140
7:4 DID 3 WUON 2 WUDR 1 DCDET 0 MCDR
15 CLDFLG
14 PFFLG
13 RSTFLG
12 NBFLG
11 UBUSY1
10 DCD
9 DSR
8 CTS
23 UTXFF1
22 URXFE1
21:16 RTCDIV
31:30 VERID
29 ID
28 BOOTBIT1
27 BOOTBIT0
26 SSIBUSY
25 CTXFF
24 CRXFE
The system status flags register is a 32-bit read only register, which indicates various system information. The bits in the system status flags register SYSFLG are defined in the following table.
Bit
0
Description
MCDR: Media changed direct read. This bit reflects the INVERTED non-latched status of the media changed input. DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is the inverted state of the NEXTPWR input pin). WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal. WUON: This bit will be set if the system has been brought out of the Standby State by a rising edge on the wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY locations. DID: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The state of the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last state of these lines before the LCD controller was enabled. These bits identify the LCD display panel fitted. CTS: This bit reflects the current status of the clear to send (CTS) modem control input to UART1. DSR: This bit reflects the current status of the data set ready (DSR) modem control input to UART1. DCD: This bit reflects the current status of the data carrier detect (DCD) modem control input to UART1. UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is guaranteed to remain set until the complete byte has been sent, including all stop bits. NBFLG: New battery flag. This bit will be set if a low to high transition has occurred on the NBATCHG input, it is cleared by writing to the STFCLR location. RSTFLG: Reset flag. This bit will be set if the RESET button has been pressed, forcing the NURESET input low. It is cleared by writing to the STFCLR location.
1
2 3
4:7
8 9 10 11
12
13
DS352PP3 JUL 2001
Register Descriptions
91
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
14
Description
PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the NPWRFL input pin, it is cleared by writing to the STFCLR location. CLDFLG: Cold start flag. This bit will be set if the EP7211 has been reset with a power on reset, it is cleared by writing to the STFCLR location. RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last increment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output. URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding register is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty. UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full. CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty. CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full. SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in or out of the synchronous serial interface, when clear data is valid to read. BOOTBIT0-1: These bits indicate the default (power-on reset) bus width of the ROM interface. See the memory configuration register for more details on the ROM interface bus width. The state of these bits reflect the state of Port E bits 0-1 during power on reset, as shown in the table below.
15
16:21
22
23
24 25 26
27
PE1 (Bootbit1)
0 0 1 1
PE0 (Bootbit0)
0 1 0 1
Boot option
32-bit 8-bit 16-bit Reserved
28 30:31
ID: Will always read `1' for the EP7211 device. VERID: Version ID bits. These 2 bits determine the version id for the EP7211. Will read `10' for the initial version.
92
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.2.5
SYSFLG2 System Status Register 2
ADDRESS: 0x8000.1140
7 Reserved 6 CKMODE 5 SS2TXUF 4 SS2TXFF 3 SS2RXFE 2 RESFRM 1 RESVAL 0 SS2RXOF
15 Reserved
14 Reserved
13 Reserved
12 Reserved
11 UBUSY2
10 Reserved
9 Reserved
8 Reserved
23 UTXFF2
22 URXFE2
21:16 Reserved
This register is an extension of SYSFLG1, containing status bits for backward compatibility with CL-PS7111. The bits of the second system status register are defined below.
Bit
11
Description
UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is guaranteed to remain set until the complete byte has been sent, including all stop bits. URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the RX holding register contains is empty. If the FIFO is enabled the URXFE bit will be set when the RX FIFO is empty. UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX FIFO is full. SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is empty. SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to transmit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data. SS2TXFF: Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This will get cleared when data is removed from the FIFO or the EP7211 is reset. SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a full RX FIFO (i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one of two ways: 1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location. 2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock cycle after it is disabled) RESVAL: Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual byte into the SSI2 RX FIFO or by a new RX frame sync pulse. RESFRM: Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame sync pulse. CKMODE: This bit reflects the status of the CLKSEL (Port E Bit 2) input, latched during NPOR. When low, the PLL is running and the chip is operating in 18.432-73.728 MHz mode. When high the chip is operating from an external 13 MHz clock.
22
23
3 5
4
0
1
2 6
DS352PP3 JUL 2001
Register Descriptions
93
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3 5.3.1
Interrupt Registers INTSR1 Interrupt Status Register 1
ADDRESS: 0x8000.0240
7 EINT3 6 EINT2 5 EINT1 4 CSINT 3 MCINT 2 WEINT 1 BLINT 0 EXTFIQ
15 SSEOTI
14 UMSINT
13 URXINT1
12 UTXINT1
11 TINT
10 RTCMI
9 TC2OI
8 TC1OI
The interrupt status register is a 32-bit read only register. The interrupt status register reflects the current state of the first 16 interrupt sources within the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.
Bit
0
Description
EXTFIQ: External fast interrupt. This interrupt will be active if the NEXTFIQ input pin is forced low and is mapped to the FIQ input on the ARM720T processor. BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (NEXTPWR is high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with a 16 kHz clock, so it will only generate an interrupt if it is active for longer than 61 s. It is mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI location. NOTE: BLINT is disabled during the Standby State. WEINT: Watch dog expired interrupt. This interrupt will become active on a rising edge of the periodic 64 Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not been serviced for a complete tick period). It is mapped to the FIQ input on the ARM720T processor and the TEOI location NOTE: WEINT is disabled during the Standby State. Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728-18.432 MHz modes). NOTE: Watchdog timer is turned off during the Standby State.
1
2
3
MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the NMEDCHG input pin has been detected, This input is de-glitched with a 16 kHz clock so it will only generate an interrupt if it is active for longer than 61 s. It is mapped to the FIQ input on the ARM7TDMI processor and is cleared by writing to the MCEOI location. On power-up, the Media change pin (NMEDCHG) is used as an input to force the processor to either boot from the internal Boot ROM, or from external memory. After power-up, the pin can be used as a general purpose FIQ interrupt pin. CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty (depending on the interface direction). It is cleared by writing to the COEOI location. EINT1: External interrupt input 1. This interrupt will be active if the NEINT1 input is active (low) it is cleared by returning NEINT1 to the passive (high) state. EINT2: External interrupt input 2. This interrupt will be active if the NEINT2 input is active (low) it is cleared by returning NEINT2 to the passive (high) state.
4
5
6
94
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
7
Description
EINT3: External interrupt input 3. This interrupt will be active if the EINT3 input is active (high) it is cleared by returning EINT3 to the passive (low) state. TC1OI: TC1 under flow interrupt. This interrupt becomes active on the next falling edge of the timer counter 1 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the TC1EOI location. TC2OI: TC2 under flow interrupt. This interrupt becomes active on the next falling edge of the timer counter 2 clock after the timer counter has under flowed (reached zero). It is cleared by writing to the TC2EOI location. RTCMI: RTC compare match interrupt. This interrupt becomes active on the next rising edge of the 1 Hz realtime clock (one second later) after the 32-bit time written to the real time clock match register exactly matches the current time in the RTC. It is cleared by writing to the RTCEOI location. TINT: 64 Hz tick interrupt. This interrupt becomes active on every rising edge of the internal 64 Hz clock signal. This 6 4Hz clock is derived from the 15-stage ripple counter that divides the 32.768 kHz oscillator input down to 1 Hz for the realtime clock. This interrupt is cleared by writing to the TEOI location. NOTE: TINT is disabled/turned off during the Standby State. UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1 bit rate and line control register), this interrupt will be active when there is no data in the UART1 TX data holding register and be cleared by writing to the UART1 data register. If the FIFO is enabled this interrupt will be active when the UART1 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full. URXINT1: Internal UART1 receive FIFO half full interrupt. The function of this interrupt source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is valid RX data in the UART1 RX data holding register and be cleared by reading this data. If the FIFO is enabled this interrupt will be active when the UART1 RX FIFO is half or more full or if the FIFO is non empty and no more characters have been received for a three character time out period. It is cleared by reading all the data from the RX FIFO. UMSINT: Internal UART1 modem status changed interrupt. This interrupt will be active if either of the two modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI location. SSEOTI: Synchronous serial interface end of transfer interrupt. This interrupt will be active after a complete data transfer to and from the external ADC has been completed. It is cleared by reading the ADC data from the SYNCIO register.
8
9
10
11
12
13
14
15
DS352PP3 JUL 2001
Register Descriptions
95
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3.2
INTMR1 Interrupt Mask Register 1
ADDRESS: 0x8000.0280
7 EINT3 6 EINT2 5 EINT1 4 CSINT 3 MCINT 2 WEINT 1 BLINT 0 EXTFIQ
15 SSEOTI
14 UMSINT
13 URXINT
12 UTXINT
11 TINT
10 RTCMI
9 TC2OI
8 TC1OI
This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of the first 16 interrupt sources within the EP7211. The four shaded interrupts all generate a fast interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will cause a jump to processor virtual address 0000.00018. Setting the appropriate bit in this register enables the corresponding interrupt. All bits are cleared by a system reset. Please refer to the INTSR1 register for individual bit details 5.3.3 INTSR2 Interrupt Status Register 2
ADDRESS: 0x8000.1240
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 SS2TX 1 SS2RX 0 KBDINT
15 Reserved
14 Reserved
13 URXINT2
12 UTXINT2
11 Reserved
10 Reserved
9 Reserved
8 Reserved
This register is an extension of INTSR1, containing status bits for backward compatibility with CLPS7111. The interrupt status register also reflects the current state of the new interrupt sources within the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.
Bit
0
Description
KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the logical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register. The interrupt request is latched, and can be de-asserted by writing to the KBDEOI location. NOTE: KBDINT is not deglitched.
1
SS2RX: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is generated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one SSI2 clock after RX is disabled.
96
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
2
Description
SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is generated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the FIFO with more data or disabling the TX. One synchronization clock required when disabling the TX side before it takes effect. UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate and line control register), this interrupt will be active when there is no data in the UART2 TX data holding register and be cleared by writing to the UART2 data register. If the FIFO is enabled this interrupt will be active when the UART2 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full. URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled this interrupt will be active when there is valid RX data in the UART2 RX data holding register and be cleared by reading this data. If the FIFO is enabled this interrupt will be active when the UART2 RX FIFO is half or more full or if the FIFO is non empty and no more characters have been received for a three character time out period. It is cleared by reading all the data from the RX FIFO.
12
13
5.3.4
INTMR2 Interrupt Mask Register 2
ADDRESS: 0x8000.1280
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 SS2TX 1 SS2RX 0 KBDINT
15 Reserved
14 Reserved
13 URXINT2
12 UTXINT2
11 Reserved
10 Reserved
9 Reserved
8 Reserved
This register is an extension of INTMR1, containing interrupt mask bits for the backward compatibility with the CL-PS7111. Please refer to INTSR2 for individual bit details. 5.3.5 INTSR3 Interrupt Status Register 3
ADDRESS: 0x8000.2240
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 MCPINT
This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the EP7211. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given below.
Bit
0
Description
MCPINT: MCP interface interrupt. The cause must be determined by reading the MCP status register. It is mapped to the FIQ interrupt on the ARM720T processor
DS352PP3 JUL 2001
Register Descriptions
97
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.3.6
INTMR3 Interrupt Mask Register 3
ADDRESS: 0x8000.2280
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 MCPINT
This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new features of the EP7211. Please refer to INTSR3 for individual bit details. 5.4 5.4.1 Memory Configuration Registers MEMCFG1 Memory Configuration Register 1
ADDRESS: 0x8000.0180
31 NCS3 configuration 24 23 NCS2 configuration 16 15 NCS1 configuration 8 7 NCS0 configuration 0
Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (CS6) is used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum wait state operation. CS7 is used for the on-chip Boot ROM and the configuration field is hardwired for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either CS6 or CS7 will be ignored. Two of the chip selects (NCS4 and 5) can be used to access two CL-PS6700 PC CARD controller devices, and when either of these interfaces is enabled, the configuration field for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2 control bit in the SYSCON2 register is disabled, then NCS4 and NCS5 are active as normal and can be programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the six external chip selects are active for 256 Mbytes and the timing and bus transfer width can be programmed individually. This is accomplished by programming the six byte-width fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a system reset (except for the CS6 and CS7 configurations). The memory configuration register 1 is a 32-bit read/write register which sets the configuration of the four expansion and ROM selects NCS0-NCS3. Each select is configured with a 1-byte field starting with expansion select 0.
98
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.4.2
MEMCFG2 Memory Configuration Register 2
ADDRESS: 0x8000.01C0
31 (Boot ROM) 24 23 (Local SRAM) 16 15 NCS5 configuration 8 7 NCS4 configuration 0
The memory configuration register 2 is a 32-bit read/write register which sets the configuration of the two expansion and ROM selects NCS4-NCS5. Each select is configured with a 1-byte field starting with expansion select 4. Each of the six non-reserved byte fields for chip select configuration in the memory configuration registers are identical and define the number of wait states, the bus width, enable EXPCLK output during accesses and enable sequential mode access. This byte field is defined below. This arrangement applies to NCS0-3, and NCS4-5 when the PC CARD enable bits in the SYSCON2 register are not set. The state of these bits is ignored for the Boot ROM and local SRAM fields in the MEMCFG2 register.
7 CLKENB 6 SQAEN 5 2 1 Bus width 0
Wait States Field
Table 5-4.Values of the Bus Width Field defines the bus width field. Note that the effect of this field is dependent on the two BOOTBIT bits that can be read in the SYSFLG register. All bits in the memory configuration register are cleared by a system reset and the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the EP7211 during power-on reset. The state of PE1 and PE0 determine whether the EP7211 is going to boot from either 32-bit wide, 16-bit wide or 8-bit wide ROMs.
Table 5-4. Values of the Bus Width Field
Bus Width Field
00 01 10 11 00 01 10 11 00 01 10
BOOTBIT1
0 0 0 0 0 0 0 0 1 1 1
BOOTBIT0
0 0 0 0 1 1 1 1 0 0 0
Expansion Transfer Mode
32-bit wide bus access 16-bit wide bus access 8-bit wide bus access Reserved 8-bit wide bus access Reserved 32-bit wide bus access 16-bit wide bus access 16-bit wide bus access 32-bit wide bus access Reserved
Port E bits 1,0 during NPOR reset
Low, Low Low, Low Low, Low Low, Low Low, High Low, High Low, High Low, High High, Low High, Low High, Low
DS352PP3 JUL 2001
Register Descriptions
99
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-4. Values of the Bus Width Field (cont.)
Bus Width Field
11
BOOTBIT1
1
BOOTBIT0
0
Expansion Transfer Mode
8-bit wide bus access
Port E bits 1,0 during NPOR reset
High, Low
The table below show the values for the wait states for random and sequential wait states at 13 and 18 MHz bus rates.
Table 5-5. Values of the Wait State Field at 13 MHz and 18 MHz
Value
00 01 10 11
No. of Wait States Random
4 3 2 1
No. of Wait States Sequential
3 2 1 0
At 36 MHz bus rate, the encoding becomes more complex:
Table 5-6. Values of the Wait State Field at 36 MHz
Bit 3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Bit 2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
Bit 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Bit 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Wait States Random
8 7 6 5 4 3 2 1 8 7 6 5 4 3 2
Wait States Sequential
3 3 3 3 2 2 2 2 1 1 1 1 0 0 0
100
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-6. Values of the Wait State Field at 36 MHz (cont.)
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
Wait States Random
1
Wait States Sequential
0
The previous table preserves compatibility with the previous devices, while allowing the previously unused bit combinations to specify more variations of random and sequential wait states.
Bit
6
Description
SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a quad word boundary to take advantage of faster access times from devices that support page mode. The sequential access will be faulted after four words, (to allow video refresh cycles to occur) even if the access is part of a longer sequential access. In addition, when this bit is not set, non-sequential accesses will have a single idle cycle inserted at least every four cycles so that the chip select is de-asserted periodically between accesses for easier debug. CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to the selected expansion device. This will provide a timing reference for devices that need to extend bus cycles using the EXPRDY input. Back to back (but not necessarily page mode) accesses will result in a continuous clock. This bit will only affect EXPCLK when the PLL is being used (i.e., in 73.728-18.432MHz mode). When operating in 13 MHz mode, the EXPCLK pin is an input so cannot be affected by this register bit. To save power internally, it should always be set to zero when operating in 13 MHz mode.
7
See the AC Electrical Specification section for more detail on bus timing. The memory area decoded by CS6 is reserved for the on-chip SRAM, hence this does not require a configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses. For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses. Chip selects NCS4 and NCS5 are used to select two CL-PS6700 PC CARD controller devices. These have a multiplexed 16-bit wide address/data interface, and the configuration bytes in the MEMCFG2 register have no meaning when these interfaces are enabled. 5.4.3 DRFPR DRAM Refresh Period Register
ADDRESS: 0x8000.0200
7 RFSHEN 6:0 RFDIV
The DRAM refresh period register is an 8-bit read/write register which enables refreshes and selects the refresh period used by the DRAM controller for its periodic CAS before RAS refresh. The value
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Register Descriptions
101
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
in the DRAM refresh period register is only cleared by a power-on reset (i.e., its state is maintained during a power fail or user reset).
Bit
7
Description
RFSHEN: DRAM Refresh enable. Setting this bit enables periodic refresh cycles to be generated by the EP7211 at a rate set by the RFDIV field. Setting this bit also enables self refresh mode when the EP7211 is in the Standby State. RFDIV: This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a 128 kHz clock and is given by the formula: Frequency (kHz) = 128 / (RFDIV + 1) i.e., RFDIV = (128 / Refresh frequency (kHz)) - 1 This equation is valid for both 13 MHz and 18.432-73.728 Mhz modes. The equation for frequency gives the refresh rate for the DRAM. The maximum refresh frequency is 64 kHz: the minimum is 1 kHz. The RFDIV field should not be programmed with zero as this will result in no refresh cycles being initiated. These values are valid for both 13 MHz and 18.432-73.728 MHz modes of operation.
0:6
5.5 5.5.1
Timer/Counter Registers TC1D Timer Counter 1 Data Register
ADDRESS: 0x8000.0300 The timer counter 1 data register is a 16-bit read/write register which sets and reads data to TC1. Any value written will be decremented on the next rising edge of the clock. 5.5.2 TC2D Timer Counter 2 Data Register
ADDRESS: 0x8000.0340 The timer counter 2 data register is a 16-bit read/write register which sets and reads data to TC2. Any value written will be decremented on the next rising edge of the clock. 5.5.3 RTCDR Realtime Clock Data Register
ADDRESS: 0x8000.0380 The real time clock data register is a 32-bit read/write register, which sets and reads the binary time in the RTC. Any value written will be incremented on the next rising edge of the 1 Hz clock. This register is reset only by NPOR. 5.5.4 RTCMR Realtime Clock Match Register
ADDRESS: 0x8000.03C0 The Realtime Clock match register is a 32-bit read/write register, which sets and reads the binary match time to RTC. Any value written will be compared to the current binary time in the RTC, if they match it will assert the RTCMI interrupt source. This register is reset only by NPOR.
102
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.6
LEDFLSH Register ADDRESS: 0x8000.22C0 The LEDFLSH register is as follows:
6 Enable 5 Duty ratio 2 1 Flash rate 0
The output is enabled whenever LEDFLSH[6] = 1. When enabled, Port D's Bit 0 Direction Register needs to be configured as an output pin and the bit cleared to `0'. When the LED Flasher is disabled, the pin defaults to being used as Port D Bit 0. Thus, this will ensure that the LED will be off when disabled. The flash rate is determined by the LEDFLSH[1:0] bits, in the following way:
Table 5-7. LED Flash Rates
LEDFLSH[1:0]
00 01 10 11
Flash Period (sec)
1 2 3 4
Table 5-8. LED Duty Ratio
LEDFLSH[5:2]
0000 0001 0010 0011 0100 0101 0110 0111
Duty Ratio (mark:space)
01:15 02:14 03:13 04:12 05:11 06:10 07:09 08:08
LEDFLSH[5:2]
1000 1001 1010 1011 1100 1101 1110 1111
Duty Ratio (mark:space)
09:07 10:06 11:05 12:04 13:03 14:02 15:01 16:00 (continually on)
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Register Descriptions
103
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.7
PMPCON Pump Control Register ADDRESS: 0x8000.0400
11:8 Drive 1 pump ratio 7:4 Drive 0 from AC source ratio 3:0 Drive 0 from battery ratio
The Pulse Width Modulator (PWM) pump control register is a 16-bit read/write register which sets and controls the variable mark space ratio drives for the two PWMs. All bits in this register are cleared by a system reset. (The top four bits are unused. They should be written as zeroes, and will read as undefined).
Bit
0:3
Description
Drive 0 from battery: This 4-bit field controls the `on' time for the drive0 PWM pump while the system is powered from batteries. Setting these bits to 0 disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source. Drive 0 from AC: This 4-bit field controls the `on' time for the drive0 DC to DC pump while the system is powered from a non-battery type power source. Setting these bits to 0 disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source. NOTE: The EP7211 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to determine which of the above fields to use. Drive 1 pump ratio: This 4-bit field controls the `on' time for the drive1 PWM pump. Setting these bits to 0 disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz source.
4:7
8:11
The state of the output drive pins is latched during power on reset, this latched value is used to determine the polarity of the drive output. The sense of the PWM control lines is summarized in Table 5-9.
Table 5-9. Sense of PWM control lines
Initial State of Driven During Power on Reset
Low High
Sense of Driven
Active high Active low
Polarity of Bias Voltage
+ve -ve
External input pins that would normally be connected to the output from comparators monitoring the PWM output are also used to enable these clocks. These are the FB[0:1] pins. They are read upon power-up. When FB[0] is high, the PWM is disabled. The same applies to FB[1].
NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs, instead of the FB pins. The clocks that source the PWMs are disable when the drive ratio fields are zeroed.
104
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.8
CODR -- The CODEC Interface Data Register ADDRESS: 0x8000.0440 The CODR register is an 8-bit read/write register, to be used with the codec interface when this is selected by the appropriate setting of Bit 0 (SERSEL) of the SYSCON2 register. Data written to or read from this register is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is then serialized and sent to or received from the codec sound device. When the codec is enabled, the codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the state of the FIFOs can be read in the system flags register. The net data transfer rate to/from the codec device is 8 kBps, giving an interrupt rate of 1 kHz.
5.9 5.9.1
UART Registers UARTDR1-2 UART1-2 Data Registers
ADDRESS: 0x8000.0480 and 0x8000.1480
10 OVERR 9 PARERR 8 FRMERR 7:0 RX data
The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the internal UARTs 1 and 2. Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled. If not it is stored in a one byte holding register. This write will initiate transmission from the UART. The UART data read registers are made up of the 8-bit data byte received from the UART together with three bits of error status. Data read from this register is popped from the 16 byte data RX FIFO, if the FIFO is enabled. If not it is read from a one byte buffer register containing the last byte received by the UART. Data received and error status is automatically pushed onto the RX FIFO if it is enabled. The RX FIFO is 10-bits wide by 16 deep.
NOTE: These registers should be accessed as words Bit
8
Description
FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiving the associated data byte. Framing errors are caused by non-matching word lengths or bit rates. PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the data byte. OVERR: UART over-run error. This bit is set if more data is received by the UART and the FIFO is full. The overrun error bit is not associated with any single character, and so is not stored in the FIFO, if this bit is set the entire contents of the FIFO is invalid and should be cleared. This error bit is cleared by reading the UARTDR register.
9
10
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Register Descriptions
105
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.9.2
UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers
ADDRESS: 0x8000.04C0 and 0x8000.14C0
31:19 18:17 WRDLEN 16 FIFOEN 15 XSTOP 14 EVENPRT 13 PRTEN 12 BREAK 11:0 Bit rate divisor
The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers sets the bit rate and mode of operation for the internal UARTs.
Bit
0:11
Description
Bit rate divisor: This 12-bit field sets the bit rate. If the system is operating from the PLL clock, then the bit rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided internally by 16 to give the bit rate. The formula to give the divisor value for any bit rate when operating from the PLL clock is: Divisor = (230400/bit rate divisor) - 1. A value of zero in this field is illegal when running from the PLL clock. The tables below show some example bit rates with the corresponding divisor value. In 13 MHz mode, the clock frequency fed to the UART is 1.8571 MHz. In this mode, zero is a legal divisor value, and will generate the maximum possible bit rate. The tables below show the bit rates available for both 18.432 MHz and 13 MHz operation.
Table 5-10. UART Bit Rates Running from the PLL Clock
Table 5-11. UART Bit Rates Running from an External 13.0 MHz Clock
Divisor Value
0 1 2 3 5 11 15 23 95 191 2094
Bit Rate Running From the Pll Clock
-- 115200 76800 57600 38400 19200 14400 9600 2400 1200 110
Divisor Value
0 1 2 5 7 11 47 96 1054
Bit Rate at 13 Mhz
116071 58036 38690 19345 14509 9673 2418 1196 110.02
Error on 13 Mhz Value
0.75% 0.75% 0.75% 0.75% 0.75% 0.75% 0.42% 0.28% 0.18%
12 13
BREAK: Setting this bit will drive the TX output active (high) to generate a break. PRTEN: Parity enable bit. Setting this bit enables parity detection and generation
106
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
14
Description
EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity, clearing it sets odd parity. This bit has no effect if the PRTEN bit is clear. XSTOP: Extra stop bit. Setting this bit will cause the UART to transmit two stop bits after each data byte, clearing it will transmit one stop bit after each data byte. FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its depth to one byte). WRDLEN: This two bit field selects the word length according to the table below.
15
16
17:18
WRDLEN
00 01 10 11
Word Length
5 bits 6 bits 7 bits 8 bits
5.10 LCD Registers 5.10.1 LCDCON -- The LCD Control Register ADDRESS: 0x8000.02C0
31 GSMD 30 GSEN 29:25 AC prescale 24:19 Pixel prescale 18:13 Line length 12:0 Video buffer size
The LCD control register is a 32-bit read/write register that controls the size of the LCD screen and the operating mode of the LCD controller. Refer to the system description of the LCD controller for more information on video buffer mapping. The LCDCON register should only be reprogrammed when LCD controller is disabled.
Bit
0:12
Description
Video buffer size: The video buffer size field is a 13-bit field that sets the total number of bits x 128 (quad words) in the video display buffer. This is calculated from the formula: Video buffer size = (Total bits in video buffer / 128) - 1 e.g., for a 640 x 240 LCD and 4-bits per pixel, the size of the video buffer = 640 x 240 x 4 = 614400 bits Video buffer size field = (614400 / 128) - 1 = 4799 or 0x12BF hex. The minimum value allowed is 3 for this bit field.
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Register Descriptions
107
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Bit
13:18
Description
Line length: The line length field is a 6-bit field that sets the number of pixels in one complete line. This field is calculated from the formula: line length = (No. pixels in line / 16) - 1 e.g., for 640 x 240 LCD Line length = (640 / 16) - 1 = 39 or 0x27 hex. The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value). Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel rate is always derived from a 36.864 MHz clock and is calculated from the formula: Pixel rate (MHz) = 36.864 / (Pixel prescale + 1) When the EP7211 is operating at 13 MHz, pixel rate is given by the formula: Pixel rate (MHz) = 13 / (Pixel prescale + 1) The pixel prescale value can be expressed in terms of the LCD size by the formula: When the EP7211 is operating @ 18.432 MHz: Pixel prescale = (36864000 / (Refresh Rate *Total pixels in display)) - 1 When the EP7211 is operating @ 13 MHz: Pixel prescale = (13000000 / (Refresh Rate * Total pixels in display)) - 1 Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker) The value should be rounded down to the nearest whole number and zero is illegal and will result in no pixel clock. EXAMPLE: For a system being operated in the 18.432-73.728 MHz mode, with a 640 x 240 screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals 36.864E6/(70 * 640x240) - 1 = 2.428 Rounding 2.428 down to the nearest whole number equals 2. This gives an actual pixel rate of 36.864E6 / 2+1 = 12.288 MHz Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz. NOTE: As the CL2 low pulse time is doubled after every CL1 high pulse this refresh frequency is only an approximation, the accurate formula is 12.288E6/((640x240)+120) = 79.937 Hz.
19:24
25:29
AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This frequency is the required AC bias frequency for a given manufacturer's LCD plate. This frequency is derived from the frequency of the line clock (CL1). The m signal will toggle after n+1 counts of the line clock (CL1) where n is the number programmed into the AC prescale field. This number must be chosen to match the manufacturer's recommendation. This is normally 13, but must not be exactly divisible by the number of lines in the display. GSEN: Grey scale enable bit. Setting this bit enables grey scale output to the LCD. When this bit is cleared each bit in the video map directly corresponds to a pixel in the display. GSMD: Grey scale mode bit. Clearing this bit sets the controller to 2-bits per pixel (4 grey scales), setting it sets it to 4 bits per pixel (16 grey scales). This bit has no effect if GSEN is cleared.
30
31
108
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.10.2 PALLSW Least Significant Word -- LCD Palette Register ADDRESS: 0x8000.0580
.
31-28 Grey scale value for pixel value 7
27-24 Grey scale value for pixel value 6
23-20 Grey scale value for pixel value 5
19-16 Grey scale value for pixel value 4
15-12 Grey scale value for pixel value 3
11-8 Grey scale value for pixel value 2
7-4 Grey scale value for pixel value 1
3-0 Grey scale value for pixel value 0
The least and most significant word LCD palette registers make up a 64-bit read/write register which maps the logical pixel value to a physical grey scale level. The 64-bit register is made up of 16 x 4bit nibbles, each nibble defines the grey scale level associated with the appropriate pixel value. If the LCD controller is operating in two bits per pixel, only the lower 4 nibbles are valid (D15-D0 in the least significant word). 5.10.3 PALMSW Most Significant Word -- LCD Palette Register ADDRESS: 0x8000.0540 See PALLSW description.
31-28 Grey scale value for pixel value 15 27-24 Grey scale value for pixel value 14 23-20 Grey scale value for pixel value 13 19-16 Grey scale value for pixel value 12 15-12 Grey scale value for pixel value 11 11-8 Grey scale value for pixel value 10 7-4 Grey scale value for pixel value 9 3-0 Grey scale value for pixel value 8
The actual physical color and pixel duty ratio for the grey scale values are shown in the table above. Note that colors 8-15 are the inverse of colors 7-0 respectively. This means that colors 7 and 8 are identical. The steps in the grey scale are non-linear, but have been chosen to give a close approximation to perceived linear grey scales. The is due to the eye being more sensitive to changes in grey level close to 50% grey.
Table 5-12. Grey Scale Value to Color Mapping
Grey Scale Value
0 1 2 3 4 5 6 7
Duty Cycle
0 1/9 1/5 4/15 3/9 2/5 4/9 1/2
% Pixels Lit
0% 11.1 % 20.0 % 26.7 % 33.3 % 40.0 % 44.4 % 50.0 %
% Step Change
11.1 % 8.9 % 6.7 % 6.6 % 6.7 % 5.4 % 5.6 % 0.0 %
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-12. Grey Scale Value to Color Mapping (cont.)
Grey Scale Value
8 9 10 11 12 13 14 15
Duty Cycle
1/2 5/9 3/5 6/9 11/15 4/5 8/9 1
% Pixels Lit
50.0 % 55.6 % 60.0 % 66.7 % 73.3 % 80.0 % 88.9 % 100 %
% Step Change
5.6 % 5.4 % 6.7 % 6.6 % 6.7 % 8.9 % 11.1 %
5.10.4 FBADDR LCD Frame Buffer Start Address ADDRESS: 0x8000.1000 This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer starts at location 0x0000000 within each chip select memory region. Therefore, the value stored within the FBADDR register is only the value of the chip select where the frame buffer is located). On reset, this will be set to 0xC for backward compatibility with the CL-PS7111. Thus the frame buffer defaults to the start of DRAM Bank 0. The register is 4 bits wide (bits [3:0]). This register must only be reprogrammed when the LCD is disabled (i.e., setting the LCDEN bit within SYSCON2 low). 5.11 SSI Register
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register ADDRESS: a0x8000.0500 SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the master only SSI. In default mode, the least significant byte is serialized and transmitted out of the synchronous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended mode, a variable number of bits are sent from SYNCIO[31:16] as determined by the ADC Configuration Length. The transfer clock will automatically be started at the programmed frequency and a synchronization pulse will be issued. The ADCIN pin is sampled on every positive going clock edge (or the falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYNCIO read register. During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will be asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the SYNCIO register is the last sixteen bits shifted out of the ADC.
110
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The length of the data frame can be programmed by writing to the SYNCIO register. This allows many different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are in multiples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data written to the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in the ADC Configuration Extension section of the SYNCIO register. In the default mode, the bits in SYNCIO have the following meaning:
31:15 Reserved 14 TXFRMEN 13 SMCKEN 12:8 Frame length 7:0 ADC Configuration Byte
Whereas in extended mode, the following applies:
15 Reserved 14 TXFRMEN 13 SMCKEN 12:7 Frame length 6:0 ADC Configuration Length
31 ADC Configuration Extension
16
NOTE: The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read bits (= 33 cycles). Bit
0:7 or 0:6
Description
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the ADC Configuration Extension field for sending to the ADC. Frame length: The Frame Length Field is the total number of shift clocks required to complete a data transfer. In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit + 16 bits result). In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result). SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC clock frequency to be output on the SMPLCK pin. TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC configuration field will be shifted out to the ADC and depending on the frame length programmed, a number of bits will be captured from the ADC. If the SYNCIO register is written to with the TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will be affected. ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0 this field is ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the SYSCON3 register = 1, this field is the configuration data to be sent to the ADC. The ADC Configuration Extension field length is determined by the value held in the ADC Configuration Length field (SYNCIO[6:0]).
8:12 or 7:12
13
14
16:31
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Register Descriptions
111
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.12 STFCLR Clear all `Start Up Reason' flags location ADDRESS: 0x8000.05C0 A write to this location will clear all the `Start Up Reason' flags in the system flags status register SYSFLG. The `Start Up Reason' flags should first read to determine the reason why the chip was started (e.g., a new battery was installed). Any value may be written to this location. 5.13 `End Of Interrupt' Locations These locations are written to after the appropriate interrupt has been serviced. The write is performed to clear the interrupt status bit, so that other interrupts can be serviced. Any value may be written to these locations. 5.13.1 BLEOI Battery Low End of Interrupt ADDRESS: 0x8000.0600 A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK with NEXTPWR high). 5.13.2 MCEOI Media Changed End of Interrupt ADDRESS: 0x8000.0640 A write to this location will clear the interrupt generated by a falling edge of the NMEDCHG input pin. 5.13.3 TEOI Tick End of Interrupt Location ADDRESS: 0x8000.0680 A write to this location will clear the current pending tick interrupt and watch dog interrupt. 5.13.4 TC1EOI TC1 End of Interrupt Location ADDRESS: 0x8000.06C0 A write to this location will clear the under flow interrupt generated by TC1. 5.13.5 TC2EOI TC2 End of Interrupt Location ADDRESS: 0x8000.0700 A write to this location will clear the under flow interrupt generated by TC2. 5.13.6 RTCEOI RTC Match End of Interrupt ADDRESS: 0x8000.0740 A write to this location will clear the RTC match interrupt
112
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt ADDRESS: 0x8000.0780 A write to this location will clear the modem status changed interrupt. 5.13.8 COEOI Codec End of Interrupt Location ADDRESS: 0x8000.07C0 A write to this location clears the sound interrupt (CSINT). 5.13.9 KBDEOI Keyboard End of Interrupt Location ADDRESS: 0x8000.1700 A write to this location clears the KBDINT keyboard interrupt. 5.13.10 SRXEOF End of Interrupt Location ADDRESS: 0x8000.1600 A write to this location clears the SSI2 RX FIFO overflow status bit. 5.14 State Control Registers 5.14.1 STDBY Enter the Standby State Location ADDRESS: 0x8000.0840 A write to this location will put the system into the Standby State by halting the main oscillator. It will automatically switch the DRAMs into self refresh if the RFSHEN bit is set in the DRAM refresh period register. All transitions to the Standby State are synchronized with DRAM cycles. A write to this location while there is an active interrupt will have no effect.
NOTE: The following restrictions apply when operating with a self-refresh DRAM 1) 2) Before entering the Standby State, the LCD Controller should be disabled. The LCD controller should be enabled on exit from the Standby State. After exiting from the Standby State, the first instruction that gets executed must be fetched from nonDRAM.
NOTE: If the EP7211 is attempting to get into the Standby State when there is a pending interrupt request, it will not enter into the low power mode. The instruction will get executed, but the processor will ignore the command.
5.14.2 HALT Enter the Idle State Location ADDRESS: 0x8000.0800 A write to this location will put the system into the Idle State by halting the clock to the processor until an interrupt is generated. A write to this location while there is an active interrupt will have no effect.
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Register Descriptions
113
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.15 SS2 Registers 5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ADDRESS: 0x8000.1500 This is the 16-bit wide data register for the full-duplex master/slave SSI2 synchronous serial interface. Writing data to this register will initiate a transfer. Writes need to be word writes and the bottom 16 bits are transferred to the TX FIFO. Reads will be 32 bits as well; the low 16 bits contain RX data and the upper 16-bits should be ignored. Although the interface is byte-oriented, data is written in two bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble the bytes for the data stream in an appropriate manner. All reads/writes to this register must be word reads/writes. 5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ADDRESS: 0x8000.16C0 This is a write-only location which will cause the contents of the RX shift register to be popped into the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is ignored. This location should be used in conjunction with the RESVAL and RESFRM bits in the SYSFLG2 register. 5.16 MCP Register Definitions There are five registers within the MCP, one control register, three data registers, and one status register. The control register is used to program the audio and telecom sample rates, to mask or unmask interrupt requests to service the MCP's FIFOs, and to select whether an on-chip or off-chip clock is used to drive the bit rate, and to enable/disable operation. The first data register addresses the top of the audio transmit FIFO and the bottom of the audio receive FIFO. Likewise, the second data register addresses the top/bottom of the telecom transmit/receive FIFOs, respectively. A read accesses the receive FIFOs, and a write the transmit FIFOs. Note that these are four physically separate FIFOs to allow full-duplex transmission. The third data register is 21 bits and is used to transmit read and write operations to the codec's control, data, and status registers. Values written to the register are used in the transmit data frame, and values read are taken from the received data frame. The status register contains bits which signal FIFO overrun and underrun errors and transmit and receive FIFO service requests. Each of these status conditions signal an interrupt request to the interrupt controller. The status register also flags when audio and telecom transmit FIFOs are not full, when the audio and telecom receive FIFOs are not empty, when a codec control register read or write is complete, and when the audio or telecom portion of the codec is enabled (no interrupt generated).
114
Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.1 MCP Control Register ADDRESS: 0x8000.2000 The MCP control register (MCCR) contains ten different bit fields that control various functions within the MCP. 5.16.1.1 Audio Sample Rate Divisor (ASD)
The 7-bit audio sample rate divisor (ASD) bit field is used to synchronize the MCP with the sample rate of the audio codec. Sample rate synchronization is required such that the MCP's audio transmit FIFO logic knows when to load a new value for D/A conversion to the MCP's serial shifter for transmission. This field is programmed with the same value that is written to the codec's sample rate divisor via a codec control register write. When the audio codec is enabled, the first audio transmit value is placed in the serial output stream by the transmit FIFO, and both the MCP's and codec's sample rate counters begin to decrement in lock-step with one another. When the audio codec's counter decrements to zero, it uses the value transmitted to it by the MCP to perform the D/A conversion. After the conversion is made, the MCP and codec's counters reset to their modulus value, and the MCP's audio transmit FIFO loads the next value to the MCP's serial shifter for transmission. This new value is then transmitted to the audio codec and is used for the next D/A conversion, which is signaled when the sample rate counter decrements to zero again. In principle, a total of 122 different audio sample rates can be selected, ranging from a minimum of 2.953 K samples per second to a maximum of 62.5 K samples per second (for a range of ASD values between 6 (00000110) and 127 (11111111)). The sample rate clock generator uses the 9.216 MHz (6.5 MHz for 13MHz mode) MCP clock, generated from a division of the chip's clock by 4, which in turn is divided by a fixed value of 32 and then the programmable ASD value to generate the audio sample clock, inside the CODEC. For instance, for the Philips UCB1100 the sampling clock is automatically enabled when: A codec control register write to the audio control register B is made (address='1000') which sets either the audio codec input or output enable bits (Bit 14 = aud_in_ena, Bit 15 = aud_out_ena) of this register, followed by the rising edge of the next SIBSYNC pulse, after the write has been made Once enabled, the MCP's audio sample rate counter decrements at the programmed frequency with a 50% duty cycle. The particular, the codec control register write outlined above causes the MCP's audio transmit FIFO logic to transfer the next available value to the audio data field within the serial shifter. Each time the audio sample rate counter decrements to zero, it is reloaded with its programmed ASD modulus value, triggers the audio transmit FIFO logic to transfer the next available value to the audio data field within the serial shifter, and continues to decrement. Again, taking the example of the UCB1100 codec, the MCP's audio sample rate clock is automatically disabled when: a codec control register write to the codec audio control register B is made (address='1000') which clears both the audio codec input and output enable bits (bit 14 = aud_in_ena, bit 15 = aud_out_ena), followed by the rising edge of the next SIBSYNC pulse after the write has been made. The resulting audio sample clock rate, given a specific ASD value can be
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
calculated using the equation below, where ASD is the decimal equivalent of the binary value programmed within the bit-field. Note that ASD must be programmed with a value of 6 or larger. Unpredictable results occur for ASD values smaller than 6. As mentioned elsewhere, the sample frequency is derived from the equation: Sample Rate = (MCP's serial clock frequency) / (32 x ASD) Using the MCP clock of 9.216 MHz, and an ASD value of 13, a nominal audio codec sample frequency of 22.05 kHz is achieved within an error of 0.5%. Although the existing MCP design includes a provisional input from an external clock and it can be programmed to accept an external clock, this feature is not enabled in the EP7211. 5.16.1.2 Telecom Sample Rate Divisor (TSD)
The 7-bit telecom sample rate divisor (TSD) bit field is used to synchronize the MCP with the sample rate of the telecom codec. The telecom sample rate clock is required for the same reason and works exactly like the audio sample rate clock, except for one minor difference. The valid TSD values range from 16 to 127 (instead of 6), allowing a total of 112 different audio sample rates to be selected, ranging from a minimum of 2.953 K samples per second to a maximum of 23.44 K samples per second. The resulting telecom sample clock rate, given a specific TSD value can be calculated using the equation below, where TSD is the decimal equivalent of the binary value programmed within the bitfield. Although (e.g., in the UCB1100 Philips telecom codec), the telecom divisor can be programmed with values in the range 6-127, note that TSD must be programmed with a value of 16 or larger. Unpredictable results occur for TSD values smaller than 16. As mentioned elsewhere, the sample frequency is derived from the equation: Sample Rate = (MCP's serial clock frequency) / (32 x TSD) Using a TSD modulus of 40 and the MCP's serial clock at 9.216 MHz, the exact nominal Telecom Sample Frequency of 7.2 kHz is achieved. 5.16.1.3 Multimedia Communications Port Enable (MCE)
The MCP enable (MCE) bit is used to enable and disable all MCP operation. When the MCP is disabled, all of its clocks are powered down to minimize power consumption. Note that MCE is the only control bit within the MCP that is reset to a known state. It is cleared to zero to ensure the MCP is disabled following a reset of the device. When the MCP is enabled, SCLK begins to transition and the start of the first frame is signaled by driving the SIBSYNC pin high for one SCLK period. The rising-edge of SIBSYNC coincides with the rising-edge of SCLK. As long as the MCE bit is set, the MCP operates continuously, transmitting and receiving 128 bit data frames. When the MCE bit is cleared, the MCP is disabled immediately, causing the current frame which is being transmitted to be terminated. Clearing MCE resets the MCP's FIFOs. However MCP data register 3, the control and the status registers are not reset. The user must ensure these registers are properly reconfigured before re-enabling the MCP. 116
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.1.4
A/D Sampling Mode (ADM)
The A/D sampling mode (ADM) bit selects whether the MCP takes audio and telecom data from the incoming frame only when their respective data valid bits are set or whenever the MCP's audio and telecom sample rate counters time-out, indicating that the data in the next incoming frame is valid. When ADM = 0, data is taken from the incoming frame and is placed into the audio or telecom FIFO whenever the incoming audio or telecom data valid bit is set. When ADM = 1, after the MCP is enabled, data is taken from the incoming frame when the data valid bit is set for the first time. After this point, the data valid bit is ignored, and samples are stored each time the audio or telecom sample rate counters decrement to zero. This indicates that a new A/D sample was taken and will be available in the next frame. The UCB1100 has two different modes of operation to control the setting of the audio and telecom data valid bits. In one mode, the codec only sets the data valid bit when a new A/D sample is contained within the incoming data frame. Once the data is transmitted to the MCP within a receive data frame, the data valid bit is reset to zero for subsequent data frames until a new A/D sample is triggered and transmitted to the MCP. In this mode, the user should program ADM = 0. In the other mode, the data valid bit is set once when the first A/D conversion is made and is placed in the receive data frame. However, the data valid bit remains set and the MCP cannot determine when samples are available within the incoming frame. Programming ADM = 1 prevents multiple copies of the sample to be placed in the FIFO, only storing samples when the sample rate counter times-out. 5.16.1.5 MCP Interrupt Generation
The MCP can generate four maskable interrupts and four non-maskable interrupts, as described in the sections below. Only one interrupt line is wired into the interrupt controller for the whole MCP. This interrupt is the wired OR of all eight interrupts (after masking where appropriate). The software servicing the interrupts must read the status register in the MCP to determine which source(s) caused the interrupt. It is possible to prevent any MCP sources causing an interrupt by masking the MCP interrupt in the interrupt controller register. 5.16.1.6 Telecom Transmit FIFO Interrupt Mask (TTM)
The telecom transmit FIFO interrupt mask (TTM) bit is used to mask or enable the telecom transmit FIFO service request interrupt. When TTM = 0, the interrupt is masked and the state of the telecom transmit FIFO service request (TTS) bit within the MCP status register is ignored by the interrupt controller. When TTM = 1, the interrupt is enabled and whenever TTS is set (one) an interrupt request is made to the interrupt controller. Note that programming TTM = 0 does not affect the current state of TTS or the telecom transmit FIFO logic's ability to set and clear TTS; it only blocks the generation of the interrupt request. 5.16.1.7 Telecom Receive FIFO Interrupt Mask (TRM)
The telecom receive FIFO interrupt mask (TRM) bit is used to mask or enable the telecom receive FIFO service request interrupt. When TRM = 0, the interrupt is masked and the state of the telecom receive FIFO service request (TRS) bit within the MCP status register is ignored by the interrupt
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
controller. When TRM = 1, the interrupt is enabled and whenever TRS is set (one) an interrupt request is made to the interrupt controller. Note that programming TRM = 0 does not affect the current state of TRS or the telecom receive FIFO logic's ability to set and clear TRS, it only blocks the generation of the interrupt request. 5.16.1.8 Audio Transmit FIFO Interrupt Mask (ATM)
The audio transmit FIFO interrupt mask (ATM) bit is used to mask or enable the audio transmit FIFO service request interrupt. When ATM = 0, the interrupt is masked and the state of the audio transmit FIFO service request (ATS) bit within the MCP status register is ignored by the interrupt controller. When ATM = 1, the interrupt is enabled and whenever ATS is set (one) an interrupt request is made to the interrupt controller. Note that programming ATM = 0 does not affect the current state of ATS or the audio transmit FIFO logic's ability to set and clear ATS; it only blocks the generation of the interrupt request. 5.16.1.9 Audio Receive FIFO Interrupt Mask (ARM)
The audio receive FIFO interrupt mask (ARM) bit is used to mask or enable the audio receive FIFO service request interrupt. When ARM = 0, the interrupt is masked and the state of the audio receive FIFO service request (ARS) bit within the MCP status register is ignored by the interrupt controller. When ARM = 1, the interrupt is enabled and whenever ARS is set (one) an interrupt request is made to the interrupt controller. Note that programming ARM = 0 does not affect the current state of ARS or the audio receive FIFO logic's ability to set and clear ARS; it only blocks the generation of the interrupt request. 5.16.1.10 Loop Back Mode (LBM) The loop back mode (LBM) bit is used to enable and disable the ability of the MCP's transmit and receive logic to communicate. When LBM = 0, the MCP operates normally. The transmit and receive data paths are independent and communicate via their respective pins. When LBM = 1, the output of the serial shifter (MSB) is directly connected to the input of the serial shifter (LSB) internally and control of the SIBDOUT, SIBDIN, SIBCLK, and SIBSYNC pins are given to the peripheral pin control (PPC) unit. The following figure shows the bit locations corresponding to the ten different control bit fields within the MCP control register. Note that the MCE bit is the only control bit which is reset to a known state to ensure the MCP is disabled following a reset of the device. The reset state of all other control bits is unknown and must be initialized before enabling the MCP. Writes to reserved bits are ignored and reads return zeros.
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Register Descriptions
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Address: 0x 8000 2000 Bit 31 30 29 28 27 26
MCP Control Register: MCCR 25 24 23 LBM 0 0 0 0 0 0 ? 22 ARM ? 21 ATM ? 20 TRM ? 19 TTM ?
Read/Write 18 ADM ? 17 ECS ? 16 MCE 0
Reserved Reset 0 0
Bit
15 Res.
14
13
12
11 TSD
10
9
8
7 Res.
6
5
4
3 ASD
2
1
0
Reset
0
?
?
?
?
?
?
?
0
?
?
?
?
?
?
?
Table 5-13. MCP Control Register
Bit
6-0
Name
ASD
Description
Audio Sample Rate Divisor Value (from 6 to 127) used to match the sample rate of the audio codec within the UCB1100 to time when audio D/A data should be supplied by the audio transmit FIFO. Sample Rate = (MCP Serial Clock Frequency) /(32 x ASD) Reserved Telecom Sample Rate Divisor Value (from 16 to 127) used to match the sample rate of the telecom codec within the UCB1100 to time when telecom D/A data should be supplied by the telecom transmit FIFO. Sample Rate = (MCP Serial Clock Frequency) /(32 x TSD) Reserved Multimedia Communications Port Enable 0 -- MCP operation disabled, control of the SIBDIN, SIBDOUT, SIBCLK, and SIBSYNC pins given to the SSI2/codec/MCP pin mulitiplexing logic to assign I/O pins 60-64 to another block. 1 -- MCP operation enabled Note that by default, the SSI/CODEC have precedence over the MCP in regard to the use of the I/O pins. Nevertheless, when Bit 3 (MCPSEL) of register SYSCON3 is set to 1, then the above mentioned MCP ports are connected to I/O pins 60-64. Reserved (Always write to zero.) A/D Data Sampling Mode 0 -- Audio and telecom receive data is stored to their respective FIFOs whenever their receive data valid bits are valid. 1 -- Audio and telecom receive data is stored when the receive data valid bit is set the first time, and from that point on whenever the MCP's audio and telecom sample rate counters time-out. Telecom Transmit FIFO Interrupt Mask 0 -- Telecom transmit FIFO half-full or less condition does not generate an interrupt (TTS bit ignored). 1 -- Telecom transmit FIFO half-full or less condition generates an interrupt (state of TTS sent to interrupt controller).
7 14-8
-- TSD
15 16
-- MCE
17 18
-- ADM
19
TTM
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-13. MCP Control Register (cont.)
Bit
20
Name
TRM
Description
Telecom Receive FIFO Interrupt Mask 0 -- Telecom receive FIFO half-full or more condition does not generate an interrupt (TRS bit ignored). 1 -- Telecom receive FIFO half-full or more condition generates an interrupt (state of TRS sent to interrupt controller). Audio Transmit FIFO Interrupt Mask 0 -- Audio transmit FIFO half-full or less condition does not generate an interrupt (ATS bit ignored). 1 -- Audio transmit FIFO half-full or less condition generates an interrupt (state of ATS sent to interrupt controller). Audio Receive FIFO Interrupt Mask 0 -- Audio receive FIFO half-full or more condition does not generate an interrupt (ARS bit ignored). 1 -- Audio receive FIFO half-full or more condition generates an interrupt (state of ARS sent to interrupt controller). Loop Back Mode 0 -- Normal serial port operation enabled 1 -- Output of serial shifter is connected to input of serial shifter internally and control of SIBDIN, SIBDOUT, SCLK, and SIBSYNC pins is given to the PPC unit. Reserved
21
ATM
22
ARM
23
LBM
31-24
--
5.16.2 MCP Data Registers The MCP contains three data registers: MCDR0 addresses the top entry of the audio transmit FIFO and bottom entry of the audio receive FIFO; MCDR1 addresses the top and bottom entry of the telecom transmit and receive FIFOs, respectively; and MCDR2 is used to perform reads and writes to any of the codec's sixteen registers via the MCP's serial interface. 5.16.2.1 MCP Data Register 0
ADDRESS: 0x8000.2040 When MPC Data Register 0 (MCDR0) is read, the bottom entry of the audio receive FIFO is accessed. As data is removed by the MCP's receive logic from the incoming data frame, it is placed into the top entry of the audio receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the FIFO. Data is removed by reading MCDR0, which accesses the bottom entry of the audio FIFO. After MCDR0 is read, the bottom entry is invalidated, and all remaining values within the FIFO automatically transfer down one location. When MCDR0 is written, the top-most entry of the audio transmit FIFO is accessed. After a write, data is automatically transferred down to the lowest location within the transmit FIFO which does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by the transmit logic, is loaded into the correct position within the 64-bit transmit serial shifter, then serially shifted out onto the SIBDOUT pin during subframe 0. Audio data is 12-bits wide and must be left justified by the user before writing them to the transmit FIFO (MSB of audio data corresponds to bit 16 of transmit FIFO). The lower four bits of the FIFO which are aligned within the 16-bit value are also written to MCDR0 for transmission. Nevertheless, 120
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
on the opposite data direction (towards the EP7211 SIBDIN), the UCB1100 automatically forces bits 0 through 3 to zero before transmitting the value to the MCP. Normally, the applications program will justify the received audio data inside the nominal data word (16-bit) accordingly, before using it. The following figure shows MCDR0. Note that the transmit and receive audio FIFOs are cleared when the device is reset, or by writing a zero to MCE (MCP disabled). Also, note that writes to reserved bits are ignored and reads return zeros.
Address: 0x 8000 2008 Bit 31 30 29 28 27
MCP Data Register 0: MCDR0 26 25 24 23 22 21 20 19
Read/Write 18 17 16
Reserved Reset Bit 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0
Bottom of Audio Receive FIFO Reset 0 0 0 0 0
Read Access
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved Reset Bit 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0
Top of Audio Transmit FIFO Reset 0 0 0 0 0
Write Access
Figure 5-1. MCP Data Register 0: MCDR0
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-14. MCP Data Register 0
Bit
3-0
Name
--
Description
Reserved for future enhancements Read -- Data returned, but UCB1100 currently zero fills these four bits Write -- MCP's transmit logic sends these bits, even though they are ignored by the UCB1100 Transmit/Receive Audio FIFO Data Read -- Bottom of Audio Receive FIFO data Write -- Top of Audio Transmit FIFO data Reserved
15-4
Audio Data --
31-16
5.16.2.2
MCP Data Register 1
ADDRESS: 0x8000.2080 When MPC Data Register 1 (MCDR1) is read, the bottom entry of the telecom receive FIFO is accessed. As data is removed by the MCP's receive logic from the incoming data frame, it is placed into the top entry of the telecom receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the FIFO. Data is removed by reading MCDR1, which accesses the bottom entry of the telecom FIFO. After MCDR1 is read, the bottom entry is invalidated, and all remaining values within the FIFO automatically transfer down one location. When MCDR1 is written, the top-most entry of the telecom transmit FIFO is accessed. After a write, data is automatically transferred down to the lowest location within the transmit FIFO which does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter then serially shifted out onto the SIBDOUT pin during subframe 0. Telecom data is 14-bits wide and must be left justified by the user before writing them to the transmit FIFO (MSB of telecom data corresponds to bit 16 of transmit FIFO). The lower two bits of the FIFO which are aligned within the 16-bit value are also written to MCDR1 for transmission. The UCB1100 automatically forces bits 0 and 1 to zero before transmitting the value to the MCP. The user must right justify received telecom data before using it.
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
The following figure shows MCDR1. Note that the transmit and receive telecom FIFOs are cleared when the device is reset, or by writing a zero to MCE (MCP disabled). Also, note that writes to reserved bits are ignored and reads return zeros.
Address: 0x 8000 200C Bit 31 30 29 28 27 MCP Data Register 1: MCDR1 26 25 24 23 22 21 20 19 Read/Write 18 17 16
Reserved Reset Bit 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bottom of Telecom Receive FIFO Reset 0 0 0 0 0
Read Access
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved Reset Bit 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Top of Telecom Transmit FIFO Reset 0 0 0 0 0
Write Access
Figure 5-2. MCP Data Register 1: MCDR1 Table 5-15. MCP Data Register 1
Bit
1-0
Name
--
Description
Reserved for future enhancements Read -- Data returned, but UCB1100 currently zero fills these two bits Write -- MCP's transmit logic sends these bits, even though they are ignored by the UCB1100 Transmit/Receive Telecom FIFO Data Read -- Bottom of Telecom Receive FIFO data Write -- Top of Telecom Transmit FIFO data Reserved
15-2
Telecom Data --
31-16
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.2.3
MCP Data Register 2
ADDRESS: 0x8000.20C0 MCDR2 contains 21 bits and is used to perform reads and writes to any of the UCB1100's sixteen registers. MCDR2 contains three separate fields: MCDR2[15:0] is the 16-bit register data field, MCDR2[16] is a 1-bit read/write control bit, and MCDR2[20:17] is the 4-bit register address field. A value written to MCDR2 is placed in the correct position within the 64-bit subframe 0, is transmitted to the off-chip codec, and is used to perform a read or write operation to the addressed codec register. Note that the contents of the addressed register are always returned in the receive data frame and placed in the MCDR2 registers regardless of the state of the read/write bit. Thus, for write cycles, both a write and a read occurs, and for read cycles, only a read occurs. When MCDR2 is read, the value returned from the last read or write operation which was completed to the codec is returned. A register write is performed by writing the correct value to each of the three fields within MCDR2 using one 16- or 32-bit write, ensuring that the read/write bit is set. Its contents are then transferred to the correct fields within the serial shifter on the next rising-edge of the SIBSYNC signal, and then to the codec via the SIBDOUT pin during subframe 0. The value within MCDR2[15:0] is written to the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The data written to the control register and its address are returned to the MCP during the next data frame, and are placed back within MCDR2, with the read/write bit reset to zero. For a write operation, since the addressed register is written at the end of subframe 0, the data returned during the frame in which the write occurred represents the previous contents of the register. The updated value is returned during the next data frame. A register read is performed by writing the address of the register to read while clearing the read/write bit to zero within MCDR2. Again, the data is transferred to the serial shifter on the next rising-edge of the SIBSYNC signal and is transmitted to the UCB1100 during subframe 0. Because the address and read/write control bit fields are placed near the beginning of the serial stream output, the codec performs the read immediately after the read/write bit is received (during the 41st bit of the frame) and the value contained within the addressed register is sent back to the MCP in the same data frame, and is placed within MCDR2. Once MCDR2 is written with a value to execute a read or write, the operation is performed every MCP data frame until a new value is written to the register. Thus continuous reads or writes are made to the addressed codec register until a new read or write operation is configured. The following figure shows the location of MCP data register 2. Note that the reset state of all MCDR2 bits is unknown, writes to reserved bits are ignored and reads return zeros.
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Address: 0x 8000 2010 Bit 31 30 29 28 27
MCP Data Register 2: MCDR2 26 25 24 23 22 21 20 19
Read/Write 18 17 16 0 ? ?
Reserved Reset 0 0 0 0 0 0 0 0 0 0 0
Erg Address R/W ? ? ?
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Data Value Returned by a Codec Register Read or Write Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Read Access
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16 R/W
Reserved Reset 0 0 0 0 0 0 0 0 0 0 0
Erg Address R/W ? ? ? ?
?
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Data Value to be Written to the Addressed Codec Register Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Write Access
Figure 5-3. MCP Data Register 2: MCDR2 Table 5-16. MCP Data Register 2
Bit
15-0
Name
Codec Register Read/Write Data
Description
Codec Register Read/Write Data Read -- If a codec write was last performed, contains data of previous register access, next frame contains the data which was written. If a codec read was last performed, contains data from the read register Write -- Used to specify what data to write to the addressed register, ignored for a codec register read Read/Write Read -- Returns a zero Write -- Used to control whether the addressed register is read or written (write = 1, read = 0) Codec Register Read/Write Address Read -- If a codec write was last performed, contains address of previous register access, next frame contains the address of the write. If a codec read was last performed, contains address of the register read Write -- Used to address a register to perform a read or write Reserved
16
R/W
20-17
Codec Register Read/Write Address
31-21
--
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
5.16.3 MCP Status Register ADDRESS: 0x8000.2100 The MCP Status Register (MCSR) contains bits which signal FIFO overrun and underrun errors and FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller. The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty, when a codec control register read or write is complete, and when the audio or telecom portion of the codec is enabled (no interrupt generated). Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags. Status bits are referred to as "sticky" (once set by hardware, they must be cleared by software). Writing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have corresponding mask bits in the control register and are indicated in the section headings below. Note that the user has the ability to mask all MCP interrupts by clearing the MCP bit within the interrupt controller mask register INTMR3. 5.16.3.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)
The audio transmit FIFO service request flag (ATS) is a read-only bit which is set when the audio transmit FIFO is nearly empty and requires service to prevent an underrun. ATS is set any time the audio transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data. When the ATS bit is set, an interrupt request is made unless the audio transmit FIFO interrupt request mask (ATM) bit is cleared. After the CPU fills the FIFO such that four or more locations are filled within the audio transmit FIFO, the ATS flag (and the service request and/or interrupt) is automatically cleared. 5.16.3.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt)
The audio receive FIFO service request flag (ARS) is a read-only bit which is set when the audio receive FIFO is nearly filled and requires service to prevent an overrun. ARS is set any time the audio receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or fewer (less than half full) entries of data. When the ARS bit is set, an interrupt request is made unless the audio receive FIFO interrupt request mask (ARM) bit is cleared. After six or more entries are removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is automatically cleared. 5.16.3.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt)
The telecom transmit FIFO service request flag (TTS) is a read-only bit which is set when the telecom transmit FIFO is nearly empty and requires service to prevent an underrun. TTS is set any time the telecom transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data. When the TTS bit is set, an interrupt request is made unless the telecom transmit FIFO interrupt request mask (TTM) bit is cleared. After the CPU fills the 126
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High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
FIFO such that four or more locations are filled within the telecom transmit FIFO, the TTS flag (and the service request and/or interrupt) is automatically cleared. 5.16.3.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrupt)
The telecom receive FIFO service request flag (TRS) is a read-only bit which is set when the telecom receive FIFO is nearly filled and requires service to prevent an overrun. TRS is set any time the telecom receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or fewer (less than half full) entries of data. When the TRS bit is set, an interrupt request is made unless the telecom receive FIFO interrupt request mask (TRM) bit is cleared. After six or more entries are removed from the receive FIFO, the TRS flag (and the service request and/or interrupt) is automatically cleared. 5.16.3.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, non-maskable interrupt)
The audio transmit FIFO underrun status bit (ATU) is set when the audio transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the audio transmit logic continuously transmits the last valid audio value which was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the audio transmit logic uses the new value within the FIFO for transmission. When the ATU bit is set, an interrupt request is made. 5.16.3.6 Audio Receive FIFO Overrun Status (ARO) (read/write, non-maskable interrupt)
The audio receive FIFO overrun status bit (ARO) is set when the audio receive logic attempts to place data into the audio receive FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to the ARO status bit is asserted, and the newly received data is discarded. This process is repeated for each new sample received until at least one empty FIFO entry exists. When the ARO bit is set, an interrupt request is made. 5.16.3.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, non-maskable interrupt)
The telecom transmit FIFO underrun status bit (TTU) is set when the telecom transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the telecom transmit logic continuously transmits the last valid telecom value which was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the telecom transmit logic uses the new value within the FIFO for transmission. When the TTU bit is set, an interrupt request is made. 5.16.3.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, non-maskable interrupt)
The telecom receive FIFO overrun status bit (TRO) is set when the telecom receive logic places data into the telecom receive FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to the TRO status bit is asserted, and the newly received sample is discarded.
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Register Descriptions
127
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
This process is repeated for each new piece of data received until at least one empty FIFO entry exists. When the TRO bit is set, an interrupt request is made. 5.16.3.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, non-interruptible)
The audio transmit FIFO not full flag (ANF) is a read-only bit which is set whenever the audio transmit FIFO contains one or more entries which do not contain valid data and is cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the audio transmit FIFO. This bit does not request an interrupt. 5.16.3.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, non-interruptible)
The audio receive FIFO not empty flag (ANE) is a read-only bit which is set when ever the audio receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remaining data from the receive FIFO. This bit does not request an interrupt. 5.16.3.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible)
The telecom transmit FIFO not full flag (TNF) is a read-only bit which is set when ever the telecom transmit FIFO contains one or more entries which do not contain valid data. It is cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the telecom transmit FIFO. This bit does not request an interrupt. 5.16.3.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, non-interruptible)
The telecom receive FIFO not empty flag (TNE) is a read-only bit which is set when ever the telecom receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remaining data from the receive FIFO. This bit does not request an interrupt. 5.16.3.13 Codec Write Completed Flag (CWC) (read-only, non-interruptible)
The codec write completed (CWC) flag is set after the following sequence occurs: 1) A register write command is issued to the codec by writing to MCDR2. 2) The write command is sent to the codec via subframe 0. 3) The data value is latched within the addressed codec register at the beginning of subframe 1 (the 65th bit of the frame). 4) The address and value which was written is returned to the MCP via the next subframe 0. 5) The returned value is latched in MCDR2. CWC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt. 5.16.3.14 Codec Read Completed Flag (CRC) (read-only, non-interruptible)
The codec read completed (CRC) flag is set after the following sequence occurs:
128
Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
1) A register read command is issued to the codec by writing to MCDR2. 2) The read command is sent to the codec via subframe 0. 3) The data value contained within the addressed codec register is loaded into the codec's serial shift register during subframe 0 (the 41st bit of the frame). 4) The address and value which was read is returned to the MCP via the same subframe 0. 5) The returned value is latched in MCDR2. CRC is automatically cleared when MCDR2 is read or written. This bit does not request an interrupt. 5.16.3.15 Audio Codec Enabled Flag (ACE) (read-only, non-interruptible)
The audio codec enabled (ACE) flag indicates when the audio codec input and/or output is enabled. This in turn indicates that the audio sample rate counter is enabled. This flag is set after the following sequence occurs: 1) A register write command is issued to Audio Control Register B (register 8), and either bit 14 or 15 is set (aud_in_ena or aud_out_ena) by writing to MCDR2. 2) The write command is sent to the codec via subframe 0. 3) The data value is latched within codec register 8. 4) SIBSYNC is asserted to indicate the start of the next frame. ACE is automatically cleared using the same sequence, with the exception that bit 14 and 15 are cleared, disabling both the input and output path of the audio codec. This bit does not request an interrupt. 5.16.3.16 Telecom Codec Enabled Flag (TCE) (read-only, non-interruptible)
The telecom codec enabled (TCE) flag indicates when the telecom codec input and/or output is enabled. This in turn indicates that the telecom sample rate counter is enabled. This flag is set after the following sequence occurs: 1) A register write command is issued to Telecom Control Register B (register 6), and either bit 14 or 15 is set (tel_in_ena or tel_out_ena) by writing to MCDR2. 2) The write command is sent to the codec via subframe 0. 3) The data value is latched within codec register 6. 4) SIBSYNC is asserted to indicate the start of the next frame. TCE is automatically cleared using the same sequence, with the exception, that bit 14 and 15 are cleared, disabling both the input and output path of the telecom codec. This bit does not request an interrupt. The following figure shows the bit locations corresponding to the status and flag bits within the MCP status register. MCSR contains a collection of read/write, read-only, interruptible, and noninterruptible bits (refer to the bit descriptions above). Writes to read-only bits have no effect. The
DS352PP3 JUL 2001
Register Descriptions
129
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
user must clear set status bits before enabling the MCP. Note that writes to reserved bits are ignored and reads return zeros.
Read/Write & Address: 0x 8000 2018 Bit 31 30 29 MCP Status Register: MCSR 28 27 26 25 24 23 22 21 20 19 Read-Only 18 17 16
Reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15
TCE
14
ACE
13
CRC
12
CWC
11
TNE
10
TNF
9
ANE
8
ANF
7
TRO
6
TTU
5
ARO
4
ATU
3
TRS
2
TTS
1
ARS
0
ATS
Reset
0
0
0
0
0
1
0
1
?
?
?
?
0
0
0
0
Figure 5-4. MCP Status Register: MCSR Table 5-17. MCP Control, Data and Status Register Locations
Bit
0
Name
ATS
Description
Audio Transmit FIFO Service Request Flag (read-only) 0 -- Audio transmit FIFO is more than half full (five or more entries filled) or MCP disabled 1 -- Audio transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is enabled, interrupt request signaled if not masked (if ATM = 1) Audio Receive FIFO Service Request (read-only) 0 -- Audio receive FIFO is less than half full (five or fewer entries filled) or MCP disabled 1 -- Audio receive FIFO is half full or more (six or more entries filled) and MCP operation is enabled, interrupt request signaled if not masked (if ARM = 1) Telecom Transmit FIFO Service Request Flag (read-only) 0 -- Telecom transmit FIFO is more than half full or less (four or fewer entries filled) or MCP disabled. 1 -- Telecom transmit FIFO is half full or less (four or fewer entries filled) and MCP operation is enabled, interrupt request signaled if not masked (if TTM = 1) 0 -- Telecom receive FIFO is less than half full (five or fewer entries filled) or MCP disabled. 1 -- Telecom receive FIFO is half full or more (six or more entries filled) and MCP operation is enabled, interrupt request signalled if not masked (if TRM = 1) Audio Transmit FIFO Underrun 0 -- Audio transmit FIFO has not experienced an underrun 1 -- Audio transmit logic attempted to fetch data from transmit FIFO while it was empty, request interrupt Audio Receive FIFO Overrun 0 -- Audio receive FIFO has not experienced an overrun 1 -- Audio receive logic attempted to place data into receive FIFO while it was full, request interrupt
1
ARS
2
TTS
3
TRS
4
ATU
5
ARO
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Register Descriptions
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 5-17. MCP Control, Data and Status Register Locations (cont.)
Bit
6
Name
TTU
Description
Telecom Transmit FIFO Underrun 0 -- Telecom transmit FIFO has not experienced an underrun 1 -- Telecom transmit logic attempted to fetch data from transmit FIFO while it was empty, request interrupt Telecom Receive FIFO Overrun 0 -- Telecom receive FIFO has not experienced an overrun 1 -- Telecom receive logic attempted to place data into receive FIFO while it was full, request interrupt Audio Transmit FIFO Not Full (read-only) 0 -- Audio transmit FIFO is full 1 -- Audio transmit FIFO is not full Audio Receive FIFO Not Empty (read-only) 0 -- Audio receive FIFO is empty 1 -- Audio receive FIFO is not empty Telecom Transmit FIFO Not Full (read-only) 0 -- Telecom transmit FIFO is full 1 -- Telecom transmit FIFO is not full Telecom Receive FIFO Not Empty (read-only) 0 -- Telecom receive FIFO is empty 1 -- Telecom receive FIFO is not empty Codec Write Completed (read-only) 0 -- A write to a codec register has not completed since the last time this bit was cleared 1 -- A write to a codec register has been transmitted and has updated the register Codec Read Completed (read-only) 0 -- The value read from the addressed codec register has not been returned to MCDR2 1 -- The value read from the addressed codec register is now in MCDR2 Audio Codec Enabled (read-only) 0 -- The audio codec input and output is disabled (bits 14 and 15 are 0 in Audio codec Control Reg B) 1 -- Audio codec input and/or output is enabled (bits 14 and/or 15 is 1 in Audio codec Control Reg B) Telecom Codec Enabled 0 -- The telecom codec input and output is disabled (bits 14 and 15 are 0 in Telecom codec Cntl Reg B) 1 -- Telecom codec input and/or output is enabled (bits 14 and/or 15 is 1 in Telecom codec Cntl Reg B) Reserved
7
TRO
8
ANF
9
ANE
10
TNF
11
TNE
12
CWC
13
CRC
14
ACE
15
TCE
31-16
-
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Register Descriptions
131
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
6. ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings
2.9 V 3.6 V 10 mA/pin; 100 mA cummulative -40C to +125C
DC Core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Pad Input Current Storage Temperature, No Power
6.2
Recommended Operating Conditions
2.5 V 0.2 V 2.3V - 3.6V O-I/O supply voltage 0C to +70C
DC core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Input/Output Voltage Operating Temperature
6.3
DC Characteristics All characteristics are specified at VDD = 2.5 volts and VSS = 0 volts over an operating temperature of 0C to +70C for all frequencies of operation. The current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation with the PLL switched `on'.
Table 6-1. DC Characteristics
Symbol
VIH VIL VT+ VTVhst VOH
Parameter
CMOS input high voltage CMOS input low voltage Schmitt trigger positive going threshold Schmitt trigger negative going threshold Schmitt trigger hysteresis CMOS output high voltageOutput drive 1 Output drive 2 CMOS output low voltageOutput drive 1 Output drive 2
Min
1.7 -0.3 1.6 (Typ) 0.8 0.1 VDD - 0.2 2.5 2.5
Max
VDD + 0.3 0.8 2.0 1.2 (Typ) 0.4
Unit
V V V V V V V V
Conditions
VDD = 2.5 V VDD = 2.5 V
VIL to VIH IOH = 0.1 mA OH = 4 mA OH = 12 mA IOL = -0.1 mA OL = -4 mA OL = -12 mA
VOL
0.3 0.5 0.5
V V V
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Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 6-1. DC Characteristics (cont.)
Symbol
IIN IOZ CIN COUT CI/O IDDstartup
Parameter
Input leakage current Output tri-state leakage current* Input capacitance Output capacitance Transceiver capacitance Startup current consumption
Min
Max
1
Unit
A A pF pF pF A
Conditions
VIN = VDD or GND VOUT = VDD or GND
25 8 8 8
100 10 10 10
Initial 100 ms from power up, 32 kHz oscillator not stable, POR signal at VIL, all other I/O static, VIH = VDD 0.1 V, VIL = GND 0.1 V Just 32 kHz oscillator running, all other I/O static, VIH = VDD 0.1 V, VIL = GND 0.1 V Both oscillators running, CPU static, LCD refresh active, VIH = VDD 0.1 V, VIL = GND 0.1 V All system active, running typical program
IDDstandby
Standby current consumption
4
A
IDDidle
Idle current consumption At 13 MHz At 18 MHz At 36 MHz Operating current consumption At 13 MHz At 18 MHz At 36 MHz At 49 MHz At 74 MHz Standby supply voltage TBD
mA 4.2 6 12 mA 14 20 40 50 68 V
IDDoperating
VDDstandby
Minimum standby voltage for state retention and RTC operation only
NOTE: All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V. The RTC of the EP7211 should be brought up at room temperature. This is required because the RTC OSC will NOT function properly if it is brought up at -40C. Once operational, it will continue to operate down to -40C. A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be compatible with 3.3 V powered external logic (e.g., 3.3 V DRAMs). Pull-up current = 50 A typical at VDD = 3.3 volts.
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Electrical Specifications
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
6.4
AC Characteristics All characteristics are specified at VDD = 2.3 to 2.7 volts and VSS = 0 volts over an operating temperature of 0C to +70C. Those characteristics marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD.
Table 6-2. AC Timing Characteristics
13 MHz 18/36 MHz Units Min
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Falling CS to data bus Hi-Z Address change to valid write data DATA in to falling EXPCLK setup time DATA in to falling EXPCLK hold time EXPRDY to falling EXPCLK setup time Falling EXPCLK to EXPRDY hold time Rising NMWE to data invalid hold time Sequential data valid to falling NMWE setup time Row address to falling NRAS setup time Falling NRAS to row address hold time Column address to falling NCAS setup time Falling NCAS to column address hold time Write data valid to falling NCAS setup time Write data valid from falling NCAS hold time LCD CL2 low time LCD CL2 high time LCD falling CL2 to rising CL1 delay LCD falling CL1 to rising CL2 LCD CL1 high time LCD falling CL1 to falling CL2 LCD falling CL1 to FRM toggle LCD falling CL1 to M toggle LCD rising CL2 to display data change Falling EXPCLK to address valid 0 0 0# 10 # 0# 10 # 10 -10 5 25 2 25 2 50 80 80 0 80 80 200 300 -10 -10 --
Symbol
Parameter Max
35 45 -- -- -- 50 -- 10 -- -- -- -- -- -- 3,475 3,475 25 3,475 3,475 6,950 10,425 20 20 33 #
Min
0 0 18 0 18 0 5 -10 5 25 2 25 2 50 80 80 0 80 80 200 300 -10 -10 --
Max
25 35 -- -- -- 50 -- 10 -- -- -- -- -- -- 3,475 3,475 25 3,475 3,475 6,950 10,425 20 20 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Table 6-2. AC Timing Characteristics (cont.)
13 MHz Symbol
T25 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40
18/36 MHz Units Min
5 0 925 925
Parameter Min
Data valid to falling NMWE for non sequential access only SSICLK period (slave mode) SSICLK high SSICLK low SSICLK rise/fall time SSICLK rising to RX and/or TX frame sync SSICLK rising edge to frame sync low SSICLK rising edge to TX data valid SSIRXDA data set-up time SSIRXDA data hold time SSITXFR and/or SSIRXFR period 30 40 750 5 0 925 925
Max
-- 512 1025 1025 7 528 448 80
Max
-- 512 1025 1025 7 528 448 80 ns kHz ns ns ns ns ns ns ns ns ns
30 40 750
Table 6-3. Timing Characteristics
13 MHz Symbol
tNCSRD tNCSWR tEXBST tRC tRAC tRP tCAS tCP tPC tCSR tRAS
18 MHz Min
70 70 35
36 MHz Units Min
50 50 8
Characteristics Min
Negative strobe (NCS[0-5]) zero wait state read access time Negative strobe (NCS[0-5]) zero wait state write access time Sequential expansion burst mode read access time DRAM cycle time Access time from RAS RAS precharge time CAS pulse width CAS precharge in page mode Page mode cycle time CAS set-up time for auto refresh RAS pulse width 120 120 55 230 110 110 30 20 70 20 110 -- -- -- -- -- -- -- --
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns ns
150 70 70 20 12 45 15 80 *
-- -- -- -- -- -- -- --
150 50 50 10 10 20 5 50*
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Electrical Specifications
135
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Consecutive Expansion Read Cycles with Minimum Wait
EXPCLK NCS[5:0]
W1&65'
NMOE
A[27:0] WORD
7 7
D[31:0] Bus held Data in
7
7$'5'
7
7
Data in
EXPRDY
7
7
Figure 6-1. Expansion and ROM Timing
NOTES:
1) TNCSRD = 35 ns at 36.864 MHz 70 ns at 18.432 MHz 120 ns at 13.0 MHz Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible.
136
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Sequential page mode read cycles with minimum wait
EXPCLK NCS[5:0]
NMOE
A[27:4]
W(;%67
A[3:0] WORD
0 4 8
W(;%67
7
D[31:0] EXPRDY Bus held
W(;5' 7 7
7
7
7
7
7
7
Data in
Data in
Data in
Figure 6-2. Expansion and ROM Sequential Read Timings
NOTES:
1) tEXBST = 35 ns at 36.864 MHz 70 ns at 18.432 MHz 120 ns at 13.0 MHz (Value for 36.864 MHz assumes 1 wait state.) Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible.
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Electrical Specifications
137
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Consecutive expansion write cycles with minimum wait states
EXPCLK NCS[5:0]
W1&6:5 W$':5 7
NMWE
A[27:0]
WORD
7
D[31:0] Bus held Write data
7
7
Write data
7
EXPRDY
7
Figure 6-3. Expansion and ROM Write Timings
NOTES:
1) tEXWR = 35 ns at 36.864 MHz 70 ns at 18.432 MHz 120 ns at 13.0 MHz Maximum values for minimum wait states. This time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. 3) Zero wait states for sequential writes is not permitted for memory devices which use NMWE pin, as this cannot be driven with valid timing under zero wait state conditions.
138
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
DRAM Word Read followed by Page Mode Read (EXPCLK shown for reference only)
EXPCLK
DRA[12:0]
ROW
COL
ROW
COL1
COL2
COLn
W5$6
NRAS[1:0]
W5&
7 W53
7
7
NCAS[3:0]
W&$6
7 W&3
W3&
D[31:0]
1
2
n
NMOE
NMWE
WORD/ HALFWORD WRITE
Figure 6-4. DRAM Read Cycles at 13 MHz and 18.432 MHz
NOTES:
1) tRC (Read cycle time) = 150 ns max at 18.432 MHz and 230 ns at 13 MHz 2) tRAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz 3) tRP (RAS precharge time) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz 4) tCAS (CAS pulse width) = 20 ns max at 18.432 MHz and 30 ns at 13 MHz 5) tCP (CAS precharge in page mode) = 12 ns max at 18.432 MHz and 20 ns at 13 MHz 6) tPC (Page mode cycle time) = 45 ns min at max at 18.432 MHz and 70 ns at 13 MHz Word reads shown, for byte reads only one off NCAS[3:0] will be active, NCAS0 for byte 0, etc.
DS352PP3 JUL 2001
Electrical Specifications
139
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
DRA[12:0]
ROW
COL
ROW
COL1
COL2
COLn
W5$6
NRAS[1:0]
W5&
7 W53
7
7
NCAS[3:0]
W&$6
7 W&3
W3&
D[31:0]
1
2
n
NMOE
NMWE
WORD/ HALFWORD WRITE
Figure 6-5. DRAM Read Cycles at 36 MHz
NOTES:
1) tRC (read cycle time) = 150 ns max 2) tRAS (RAS pulse width) = 70 ns max 3) tRP (RAS precharge time) = 70 ns max 4) tCAS (CAS pulse width) = 10 ns max 5) tCP (CAS precharge in page mode) = 10 ns max 6) tPC (Page mode cycle time) = 25 ns max Word reads shown, for byte reads only one off NCAS[3:0] will be active, NCAS0 for byte 0, etc.
140
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
DRA[12:0]
ROW
COL
ROW
COL1
COL2
COLn
W5$6
NRAS[1:0]
W5&
7 W53
7 7
7 W&$6
W&3
W3&
NCAS[3:0]
D[31:0]
Data Out
Data Out 1
Data Out 2
Data Out n
NMOE
NMWE
WORD/ HALFWORD WRITE
Figure 6-6. DRAM Write Cycles at 13 MHz and 18 MHz
NOTES:
1) tRC (Write cycle time) = 150 ns max at 18.432 MHz and 230 ns at 13 MHz 2) tRAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz 3) tRP (RAS precharge time) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz 4) tCAS (CAS pulse width) = 20 ns max at 18.432 MHz and 30 ns at 13 MHz 5) tCP (CAS precharge in page mode) = 66 ns max at 18.432 MHz and 140 ns at 13 MHz 6) tPC (Page mode cycle time) = 100 ns min at max at 18.432 MHz and 140 ns at 13 MHz Word writes shown, for byte writes only one off NCAS[3:0] will be active, NCAS0 for byte 0, etc.
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Electrical Specifications
141
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
DRAM Word Read followed by Page Mode Read (EXPCLK shown for reference only)
EXPCLK
DRA[12:0]
ROW
COL
ROW
COL1
COL2
COLn
W5$6
NRAS[1:0]
W5&
W53
7 7 7 7 W&$6
W&3
W3&
NCAS[3:0]
D[31:0]
Data Out 1
Data Out 2
Data Out n
NMOE
NMWE
WORD/ HALFWORD WRITE
Figure 6-7. DRAM Write Cycles at 36 MHz
NOTES:
1) tRC (Write cycle time) = 150 ns max 2) tRAS (RAS pulse width) = 70 ns max 3) tRP (RAS precharge time) = 70 ns max 4) tCAS (CAS pulse width) = 10 ns max 5) tCP (CAS precharge in page mode) = 35 ns max 6) tPC (Page mode cycle time) = 50 ns max Word reads shown, for byte reads only one off NCAS[3:0] will be active, NCAS0 for byte 0, etc.
142
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
W9$&&
EXPCLK
DRA[12:0]
ROW
COL0
COL1
COL2
COL3
W53
RAS0
CAS[3:0]
W&$6 W&3
W3&
D[31:0]
0
1
2
3
NMOE
NMWE
Figure 6-8. Video Quad Word Read from DRAM at 13 MHz and 18 MHz
NOTES:
1). Timings are the same as page mode word reads 2) tVACC (video access cycle time) = 326 ns at EXPCLK = 18.432 MHz and 462 ns at 13 MHz
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Electrical Specifications
143
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
DRA[12:0]
ROW
COL0
COL1
COL2
COL3
W53
NRAS[1:0]
79$&
W&$6 W&3
NCAS[3:0]
W3&
D[31:0]
1
2
3
4
NMOE
NMWE
Figure 6-9. Quad Word Read from DRAM at 36 MHz
NOTES:
1). Timings are the same as page mode word reads 2) tVACC (video access cycle time) = 220 ns at EXPCLK = 36 MHz 3) The filled-in grey areas are don't cares.
144
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK DRA[12:0] Held Row Col
W&6$ W5$6
RAS[3:0]
W5&
CAS[3:0]
D[31:0]
Held
NMOE
NMWE
Figure 6-10. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz
NOTES:
1). tCSA (CAS set-up time) = 15 ns max at 18.432 MHz and 20 ns at 13 MHz 2) tRAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz 3) tRC (cycle time) = 180 ns max at 18.432 MHz and 230 ns at 13 MHz When DRAMs are placed in self-refresh (entering the Standby State), the same timings, except that tRAS is extended indefinitely. 4) The filled-in grey area is a don't care.
DS352PP3 JUL 2001
Electrical Specifications
145
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
EXPCLK
DRA[12:0]
Held
Row
Col
W&6$
NRAS[1:0]
W5$6
W5&
NCAS[3:0]
D[31:0]
Held
NMOE
NMWE
Figure 6-11. DRAM CAS Before RAS Refresh Cycle at 36 MHz
NOTES:
1) tCSA (CAS set-up time) = 8 ns max 2) tRAS (RAS pulse width) = 60 ns max 3) tRC (cycle time) = 167 ns max When DRAMs are placed in self-refresh (entering the Standby State), the same timings, except that tRAS is extended indefinitely.
146
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
7
CL2
7
7
7
CL1
7
7
7
FRM
7
M
7
DD[3:0]
Figure 6-12. LCD Controller Timings
NOTES:
1) The figure shows the end of a line. 2) If FRM is high during the CL1 pulse, this marks the first line in the display. 3) CL2 low time is doubled during the CL1 high pulse
ADCCLK
NADCCS
ADCIN
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
ADCOUT
DO9
DO8
DO1
DO0
Figure 6-13. SSI Interface for AD7811/2
DS352PP3 JUL 2001
Electrical Specifications
147
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
ADCCLK

NADCCS
ADCIN
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
ADCOUT
DO15 DO14 DO13 DO12 DO11 DO10
DO1
DO0
Figure 6-14. SSI Timing Interface for MAX148/9
7
SSICLK
7
7
7
SSI RX/TXFR
7 7 7
SSITXDA
' 7 7 '
'
'
'
SSIRXDA
'
'
'
Figure 6-15. SSI2 Interface Timings
148
Electrical Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
6.5
I/O Buffer Characteristics All I/O buffers on the EP7211 are CMOS threshold input bidirectional buffers except the oscillator and power pads. For signals that are nominally inputs, the output buffer is only enabled during pin test mode. All output buffers are tristated during system (hi-Z) test mode. All buffers have a standard CMOS threshold input stage (apart from the Schmitt triggered inputs) and CMOS slew rate controlled output stages to reduce system noise. Table 6-4. I/O Buffer Output Characteristics defines the I/O buffer output characteristics which will apply across the full range of temperature and voltage (i.e., these values are for 3.3 V, +70C).
Table 6-4. I/O Buffer Output Characteristics
Buffer Type
I/O strength 1 I/O strength 2
Drive Current
4 mA 12 mA
Propagation Delay (Max)
7 5
Rise Time (Max)
14 6
Fall Time (Max)
14 6
Load
50 pF 50 pF
All propagation delays are specified at 50% VDD to 50% VDD, all rise times are specified as 10% VDD to 90% VDD and all fall times are specified as 90% VDD to 10% VDD.
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Electrical Specifications
149
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
7. TEST MODES
The EP7211 supports a number of hardware activated test modes, these are activated by the pin combinations shown in the Table 7-1. EP7211 Hardware Test Modes. All latched signals will only alter test modes while NPOR is low, their state is latched on the rising edge of NPOR. This allows these signals to be used normally during various test modes.
Table 7-1. EP7211 Hardware Test Modes
Test Mode
Normal operation (32-bit boot) Normal operation (8-bit boot) Normal operation (16-bit boot) Alternative test ROM boot Oscillator / PLL bypass Oscillator / PLL test mode ICE Mode System test (all HiZ)
Latched NMEDCHG
1 1 1 0 X X X X
Latched PE0
0 1 0 X X X X X
Latched PE1
0 0 1 X X X X X
Latched NURESET
X X X X X 0 1 0
NTEST0
1 1 1 1 1 0 0 0
NTEST1
1 1 1 1 0 1 0 0
Within each test mode, a selection of pins is used as multiplexed outputs or inputs to provide/monitor the test signals unique to that mode. 7.1 Oscillator and PLL Bypass Mode This mode is selected by NTEST0 = 1, NTEST1 = 0. In this mode all the internal oscillators and PLL are disabled and the appropriate crystal oscillator pins become the direct external oscillator inputs bypassing the oscillator and PLL. MOSCIN must be driven by a 36.864 MHz clock source and RTCIN by a 32.768 kHz source. 7.2 Oscillator and PLL Test Mode This mode is selected by NTEST0 = 0, NTEST1 = 1, Latched NURESET = 0 This test mode will enable the main oscillator and it will output various buffered clock and test signals derived from the main oscillator, PLL, and 32-kHz oscillator. All internal logic in the EP7211 will be static and isolated from the oscillators, with the exception of the 6-bit ripple counter used to generate 576 kHz and the real time clock divide chain. Port A is used to drive the inputs of the PLL directly, and the various clock and PLL outputs are monitored on the COL pins. Table 7-2.
150
Test Modes
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
Oscillator and PLL Test Mode Signals defines the EP7211 signal pins used in this test mode. This mode is only intended to allow test of the oscillators and PLL.
Table 7-2. Oscillator and PLL Test Mode Signals
Signal
TSEL * XTLON * PLLON * PLLBP RTCCLK CLK1 OSC36 CLK576K VREF
I/O
I I I I O O O O O
Pin
PA5 PA4 PA3 PA0 COL0 COL1 COL2 COL4 COL6 PLL test mode Enable to oscillator circuit Enable to PLL circuit Bypasses PLL Output of RTC oscillator
Function
1 Hz clock from RTC divider chain 36 MHz divided PLL main clock 576 KHz divided from above Test clock output for PLL
Note that these inputs are inverted before being passed to the PLL to ensure that the default state of the port (all zero) maps onto the correct default state of the PLL (TSEL = 1, XTALON = 1, PLLON = 1, D0 = 0, D1 = 1, PLLBP = 0). This state will produce the correct frequencies as shown in Table 7-2. Oscillator and PLL Test Mode Signals. Any other combinations are for testing the oscillator and PLL and should not be used in-circuit. 7.3 Debug/ICE Test Mode This mode is selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 1. Selection of this mode enables the debug mode of the ARM720T. By default, this is disabled which saves approximately 3% on power. 7.4 Hi-Z (System) Test Mode This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0. This test mode asynchronously disables all output buffers on the EP7211. This has the effect of removing the EP7211 from the PCB so that other devices on the PCB can be in-circuit tested. The internal state of the EP7211is not altered directly by this test mode. 7.5 Software Selectable Test Functionality When Bit 11 of the SYSCON register is set high, internal peripheral bus register accesses are output on the main address and data buses as though they were external accesses to the address space addressed by CS5. Hence, CS5 takes on a dual role, it will be active as the strobe for internal accesses and for any accesses to the standard address range for CS5. Additionally, in this mode, the internal
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Test Modes
151
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
signals shown in Table 7-3. Software Selectable Test Functionality are multiplexed out of the device on port pins.
Table 7-3. Software Selectable Test Functionality
Signal
CLK NFIQ NIRQ
I/O
O O O
Pin
PE0 PE1 PE2
Function
Waited clock to CPU NFIQ interrupt to CPU NIRQ interrupt to CPU
This test is not intended to be used when LCD DMA accesses are enabled. This is due to the fact that it is possible to have internal peripheral bus activity simultaneously with a DMA transfer. This would cause bus contention to occur on the external bus. The `Waited clock to CPU' is an internally ANDed source that generates the actual CPU clock. Thus, it is possible to know exactly when the CPU is being clocked by viewing this pin. The signals NFIQ and NIRQ are the two output signals from the internal interrupt controller. They are input directly into the ARM720T processor.
152
Test Modes
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
8. PACKAGE SPECIFICATIONS
8.1 EP7211 256-Ball PBGA (17 x 17 x 1.53-mm Body) Dimensions
0.80 (0.032) 0.05 (.002) 17.00 (0.669) 0.40 (0.016) 0.10 (.004)
Pin 1 Corner
+0.70 (.027) 15.00 (0.590) -0.00
30 TYP
Pin 1 Indicator 17.00 (0.669) 15.00 (0.590) +0.70 (.027) -0.00 4 Layer 0.56 (0.022) 0.06 (0.002) 2 Layer 0.36 (0.022) +0.04 (0.001) -0.06 (0.002)
TOP VIEW
SIDE VIEW
17.00 (0.669) 1.00 (0.040) 1.00 (0.040) REF
16 15 14 13 121110987654321
Pin 1 Corner
1.00 (0.040) REF
1.00 (0.040)
A B C D E F G H J K L M N P R T
17.00 (0.669)
0.50 R 3 Places
BOTTOM VIEW
(Call Factory for Availability)
DS352PP3 JUL 2001
Package Specifications
153
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
8.2
208-Pin LQFP Package Outline Drawing
29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011)
27.80 (1.094) 28.20 (1.110)
29.60 (1.165) 30.40 (1.197)
EP7211 208-Pin LQFP
0.50 (0.0197) BSC
Pin 1 Indicator
Pin 208 Pin 1
0.45 (0.018) 0.75 (0.030)
1.35 (0.053) 1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006)
0 MIN 7 MAX
NOTES:
1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
154
Package Specifications
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
9. ORDERING INFORMATION
The order number for the device is:
EP7211 -- CV -- A
Revision Package Type: V = Low Profile Quad Flat Pack P = Plastic Ball Grid Array (17 mm x 17 mm) Temperature Range: C = Commercial Part Number Product Line: Embedded Processor
NOTE: Contact Cirrus Logic for up-to-date information on revisions.
DS352PP3 JUL 2001
ORDERING INFORMATION
155
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
10. APPENDIX A: BOOT CODE
;(C) Copyright 1995-2000 , Cirrus Logic, Inc. All Rights Reserved. ; TTL ; ; CL-EP7211 Sample program version 1.0 (initial version) ;ks boot from uart1 AREA ENTRY ; ; HwBaseAddress ; ; HwControl HwControl2 HwControlUartEnable ; HwStatus HwStatus2 HwStatusUartRxFifoEmpty ; HwUartData HwUartData2 HwUartDataFrameErr HwUartDataParityErr HwUartDataOverrunErr HwUartControl HwUartControl2 HwUartControlRate HwUartControlRate115200 HwUartControlRate76800 HwUartControlRate57600 HwUartControlRate38400 HwUartControlRate19200 HwUartControlRate14400 HwUartControlRate9600 HwUartControlRate4800 HwUartControlRate2400 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0x00000480 0x00001480 0x0100 0x0200 0x0400 0x000004C0 0x000014C0 0x00000FFF 0x001 0x002 0x003 0x005 0x00B 0x00F 0x017 0x02F 0x05F EQU EQU EQU 0x00000140 0x000001140 0x00400000 EQU EQU EQU 0x00000100 0x00001100 0x00000100 EQU 0x80000000 System constants |C$$code|,CODE,READONLY
156
Appendix A: Boot Code
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
HwUartControlRate1200 HwUartControlRate600 HwUartControlRate300 HwUartControlRate150 HwUartControlRate110 HwUartControlRate115200_13 HwUartControlRate57600_13 HwUartControlRate38400_13 HwUartControlRate19200_13 HwUartControlRate14400_13 HwUartControlRate9600_13 HwUartControlRate4800_13 HwUartControlRate2400_13 HwUartControlRate1200_13 HwUartControlRate600_13 HwUartControlRate300_13 HwUartControlRate150_13 HwUartControlRate110_13 HwUartControlBreak HwUartControlParityEnable HwUartControlPartiyEvenOrOdd HwUartControlTwoStopBits HwUartControlFifoEnable HwUartControlDataLength HwUartControlDataLength5 HwUartControlDataLength6 HwUartControlDataLength7 HwUartControlDataLength8 ; ;
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
0x0BF 0x17F 0x2FF 0x5FF 0x82E 0x000 0x001 0x002 0x005 0x007 0x00b 0x017 0x02F 0x060 0x0c0 0x182 0x305 0x41E 0x00001000 0x00002000 0x00004000 0x00008000 0x00010000 0x00060000 0x00000000 0x00020000 0x00040000 0x00060000
9600baud, 8bits/ch no parity, 1 stop bit EQU EQU EQU EQU EQU EQU EQU EQU HwUartControlRate9600+HwUartControlDataLength8 HwUartControlRate9600_13+HwUartControlDataLength8 0x10000000 0x10000000 0x00000800 '<' '>' 0x40 ;clock mode 1 = 13 MHz ;start address sram snooze buffer ; ;2k bytes
UartValue UartValue_13 BufferAddress codeexeaddr count startflag endflag CLKMOD
DS352PP3 JUL 2001
Appendix A: Boot Code
157
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
;
ARM Processor constants EQU EQU 0x00000080 0x00000040
ArmIrqDisable ArmFiqDisable
; 26bit mode is not supported ; ArmUserMode ArmFIQMode ArmIRQMode ArmSVCMode ArmAbortMode ArmUndefMode ArmMaskMode ; ArmMmuCP ; ArmMmuId ; ArmMmuControl ArmMmuControlMmuEnable ArmMmuControlAlignFaultEnable ArmMmuControlCacheEnable ArmMmuControlWriteBufferEnable ArmMmuControl32BitCodeEnable ArmMmuControl32BitDataEnable ArmMmuControlMandatory ArmMmuControlBigEndianEnable ArmMmuControlSystemEnable ArmMmuControlRomEnable ; ArmMmuPageTableBase ; ArmMmuDomainAccess ; ArmMmuFlushTlb ; ArmMmuPurgeTlb CN 0x06 CN 0x05 CN 0x03 CN 0x02 CN 0x01 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0x00000001 0x00000002 0x00000004 0x00000008 0x00000010 0x00000020 0x00000040 0x00000080 0x00000100 0x00000200 CN 0x00 CP 0xF EQU EQU EQU EQU EQU EQU EQU 0x10 0x11 0x12 0x13 0x17 0x1B 0x1F
158
Appendix A: Boot Code
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
; ArmMmuFlushIdc CN 0x07 ArmMmuControl32BitCodeEnable +ArmMmuControlMandatory
;InitialMmuConfig EQU +ArmMmuControl32BitDataEnable +ArmMmuControlBigEndianEnable
InitialMmuConfig EQU ArmMmuControl32BitCodeEnable +ArmMmuControl32BitDataEnable +ArmMmuControlMandatory ;leave as little endian 11/6/96 ks ;============================================================================== ====== ; REAL CODE START
; set little endian, 32bit code, 32bit data by writing to CP15's control register LDR MCR ; MRS BIC ORR MSR ; ; LDR MOV STR LDR ADD LDR TST LDREQ LDRNE STR DS352PP3 JUL 2001 initialize HW control r12,=HwBaseAddress r0,#HwControlUartEnable r0,[r12,#HwControl] r1,=HwStatus2 r1,r1,r12 r2,[r1] r2,#CLKMOD r0,=UartValue r0,=UartValue_13 r0,[r12,#HwUartControl] ;load 18 mhz value if bit not set ;load 13 mhz value if bit set ;initialise Uart ;read system flag2 ;Enable UART r0, =InitialMmuConfig ArmMmuCP, 0, r0, ArmMmuControl, c0 set the cpu to SVC32 mode r0, CPSR r0, r0, #ArmMaskMode r0, r0, #ArmSVCMode CPSR, r0 ;read psr ;remove the mode bits ;set to supervisor 32 bit mode ; Now set the CPU into the new mode
UARTEnable
Appendix A: Boot Code
159
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
; LDR
Send ready signal r0,=startflag r0,[r12,#HwUartData] ; send ready STRB
; LDR LDR 01 ; LDR TST BNE ;
receive the data r3,=count r2,=BufferAddress
wait for byte available r1,[r12,#HwStatus] r1,#HwStatusUartRxFifoEmpty %b01 read the data ,store it and accumulate checksum LDRB STRB SUBS BNE r0,[r12,#HwUartData] r0,[r2],#1 r3,r3,#1 %b01 all received, send end flag LDR STRB LDR LTORG END r0,=endflag r0,[r12,#HwUartData] r15,=codeexeaddr ; send reply ;jump to execution address ; read data ; save it in memory ; decrement count ; do more if count has not expired ; spin, if Rx FIFO is empty
;
160
Appendix A: Boot Code
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
11. INDEX
Numerical
208-pin LQFP JTAG pin ordering 31 208-pin LQFP pin listing 26 208-pin VQFP package 155
Alphabetical B
boundary scan 78
C
clocks 73 external clock input (13 MHz) 74 on-chip PLL 73 CPU core 37
D
dedicated LED flasher 68 DRAM controller with EDO support 47
E
endianness 75
F
functional block diagram 37 functional description 34
I
idle state 40 internal UARTs 67 in-circuit emulation 79 interrupt controller 37, 72
L
LCD controller 64
M
main functional blocks 35 memory and I/O expansion interface 42 CL-EP7211 boot ROM 43 CL-PS6700 PC CARD controller interface 44 memory interfaces 2 Microwire 2
O
operating state 39
P
packaging 4 PADDR Port A Data Direction Register 85 PADR Port A Data Register 85
DS352PP3 JUL 2001
Index
161
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
PBDR Port B Data Register 85 PBGA ground connections 25 PDDDR Port D Data Direction Register 85 PDDR Port D Data Register 85 PEDDR Port E Data Direction Register 86 pin descriptions, external signal functions 15 pin diagram 13 pin diagram, 208-pin LQFP 13 pin diagram, 256-lead PBGA 14 pin information A 15 ADCCLK 17 ADCIN 17 ADCOUT 17 BATOK 16 BOOTSEL0 18 BOOTSEL1 18 BUZ 17 CL1 17 CL2 17 CLKSEL 18 COL 17 CTS 17 D 15 DCD 17 DD 17 DRA 15 DRIVE 18 DSR 17 EINT3 16 EXPCLK 15 EXPRDY 15 FB 18 FRM 17 HALFWORD 15 LEDDRV 17 LEDFLSH 17 M 17 MOSCIN 18 MOSCOUT 18 NADCCS 17 NBATCHG 16 NCAS 15 NCS 15 NEINT 16 NEXTFIQ 16 NEXTPWR 16 NMEDCHG/ BROM 16 NMOE 15 NMWE 15 NPOR 16 NPWRFL 16 NRAS 15 NTEST 18 NURESET 16 PA 17 PB 17
162
Index
DS352PP3 JUL 2001
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
PD 17 PE 18 PHDIN 17 PRDY1 17 PRDY2 PB 17 RTCIN 18 RTCOUT 18 RUN/CLKEN 16 RXD 17 SMPCLK 17 SSICLK 16 SSIRXDA 16 SSIRXFR 16 SSITXDA 16 SSITXFR 16 TCLK 18 TDI 18 TDO 18 TMS 18 TNRST 18 TXD 17 WAKEUP 16 WORD 15 WRITE 15 power management 2 PWM interface 69
prescale mode 68
U
UART 1-2, 37
R
real-time clock 68 resets 72
S
serial interface ADC Interface 60 clock polarity 64 continuous data transfer 63 discontinuous clock 63 error conditions 64 MCP CODEC control register data transfer 59 MCP FIFO operation 58 MCP interface 53 MCP operation 54 readback of residual data 62 support for asymmetric traffic 63 serial interfaces 3, 51 CODEC interrupt timing 52 CODEC sound interface 52 SIR encoder 67 SPI 2 standby state 40 state control 69 SYSFLG, The System Status Flags Register 92 system design 4
T
timer counters 67 free running mode 68
DS352PP3 JUL 2001
Index
163
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
164
Index
DS352PP3 JUL 2001
* Notes *

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